Inventor

NALAMALPU ANKIREDDY

US56 patents

⚠️ This page may combine multiple inventors who share the name “NALAMALPU ANKIREDDY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NALAMALPU ANKIREDDY

INTEL CORP

Translation circuitry for an interconnection in an active interposer of a semiconductor package

Interconnect architecture with silicon interposer and EMIB

Dual in-line memory module (DIMM) programmable accelerator card

Flexible instruction set architecture supporting varying frequencies

Selective use of different advanced interface bus with electronic chips

Innovative interconnect design for package architecture to improve latency

Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling

Apparatus to synchronize clocks of configurable integrated circuit dies through an interconnect bridge

Modular periphery tile for integrated circuit device

Modular periphery tile for integrated circuit device

Programmable logic device with fine-grained disaggregation

Techniques for clock signal transmission in integrated circuits and interposers

On-die aging measurements for dynamic timing modeling

Systems and methods for dynamic power and thermal management for programmable logic devices

Controlled transition between configuration mode and user mode to reduce current-resistance voltage drop

Switch based on load current

Interconnect architecture with silicon interposer and EMIB

Innovative interconnect design for package architecture to improve latency

Programmable logic device with fine-grained disaggregation

Modular periphery tile for integrated circuit device

Techniques for clock signal transmission in integrated circuits and interposers

Low-latency optical connection for CXL for a server CPU

Interconnect architecture with silicon interposer and EMIB

Modular periphery tile for integrated circuit device

Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package

Innovative interconnect design for package architecture to improve latency

High-speed core interconnect for multi-die programmable logic devices

Programmable logic device with fine-grained disaggregation

Rotatable architecture for multi-chip package (MCP)

High-speed core interconnect for multi-die programmable logic devices

Innovative interconnect design for package architecture to improve latency

Programmable logic device with fine-grained disaggregation

Interface bus for inter-die communication in a multi-chip package over high density interconnects

Workload-dependent integrated circuit operation based on power headroom

Dynamic loadlines for programmable fabric devices

Systems and methods to reduce voltage guardband

Network-on-chip (NOC) with flexible data width

Network-on-chip (NOC) with flexible data width

Network-on-chip (NOC) with flexible data width

Techniques for power management in compute circuits

Segmented row repair for programmable logic devices

On-die aging measurements for dynamic timing modeling

Dynamically scalable timing and power models for programmable logic devices

Processor package with universal optical input/output

Connectivity between integrated circuit dice in a multi-chip package

Electronic chip with under-side power block

Methods for handling integrated circuit dies with defects

High-speed core interconnect for multi-die programmable logic devices

Network-on-chip (NOC) with flexible data width

ALTERA CORP

Homogenous die stacking with increased element density