Inventor

HOSSAIN MD ALTAF

US54 patents

⚠️ This page may combine multiple inventors who share the name “HOSSAIN MD ALTAF”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HOSSAIN MD ALTAF

INTEL CORP

Translation circuitry for an interconnection in an active interposer of a semiconductor package

Interconnect architecture with silicon interposer and EMIB

Shared command address (C/A) bus for multiple memory channels

Flexible instruction set architecture supporting varying frequencies

Innovative interconnect design for package architecture to improve latency

Microelectronics assembly including top and bottom packages in stacked configuration with shared cooling

Modular periphery tile for integrated circuit device

Modular periphery tile for integrated circuit device

Programmable logic device with fine-grained disaggregation

Techniques for clock signal transmission in integrated circuits and interposers

Land side and die side cavities to reduce package z-height

Land side and die side cavities to reduce package z-height

Land side and die side cavities to reduce package z-height

Switch based on load current

Interconnect architecture with silicon interposer and EMIB

Innovative interconnect design for package architecture to improve latency

Programmable logic device with fine-grained disaggregation

Modular periphery tile for integrated circuit device

Techniques for clock signal transmission in integrated circuits and interposers

Low-latency optical connection for CXL for a server CPU

Interconnect architecture with silicon interposer and EMIB

Modular periphery tile for integrated circuit device

Frequency translation circuitry for an interconnection in an active interposer of a semiconductor package

Reverse-bridge multi-die interconnect for integrated-circuit packages

Innovative interconnect design for package architecture to improve latency

Programmable logic device with fine-grained disaggregation

Innovative way to design silicon to overcome reticle limit

Rotatable architecture for multi-chip package (MCP)

Innovative interconnect design for package architecture to improve latency

Programmable logic device with fine-grained disaggregation

Interface bus for inter-die communication in a multi-chip package over high density interconnects

Land side and die side cavities to reduce package z-height

Workload-dependent integrated circuit operation based on power headroom

Dynamic loadlines for programmable fabric devices

Systems and methods to reduce voltage guardband

Method for orienting solder balls on a BGA device

Techniques for power management in compute circuits

Circuit board with integrated passive devices

Processor package with universal optical input/output

Connectivity between integrated circuit dice in a multi-chip package

Electronic chip with under-side power block

Method for orienting solder balls on a BGA device

Configuration of data strobes

Self-gating flops for dynamic power reduction

Power management using voltage islands on programmable logic devices

HOSSAIN MD ALTAF

Land side and die side cavities to reduce package Z-height

Microelectronic substrate for alternate package functionality

BGA structure using CTF balls in high stress regions

TAHOE RES LTD

Method for orienting solder balls on a BGA device

ALTERA CORP

Homogenous die stacking with increased element density