Inventor

HAMMARLUND PER H

US35 patents

⚠️ This page may combine multiple inventors who share the name “HAMMARLUND PER H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAMMARLUND PER H

APPLE INC

Scalable cache coherency protocol

Multiple independent on-chip interconnect

Scalable system on a chip

Scalable cache coherency protocol

Scalable cache coherency protocol

Scalable system on a chip

Scalable cache coherency protocol

Hashing with soft memory folding

Multiple independent on-chip interconnect

Scalable system on a chip

Ensuring transactional ordering in I/O agent

Scalable system on a chip

I/O agent

Critical agent identification to modify bandwidth allocation in a virtual channel

Hashing with soft memory folding

Segment to segment network interface

Merged power delivery

Method and apparatus for ensuring real-time snoop latency

Full die and partial die tape outs from common design

INTEL CORP

Breaking replay dependency loops in a processor using a rescheduled replay queue

Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter

Method and apparatus for providing a cache management technique

Method and apparatus for rescheduling operations in a processor

Method and apparatus for variable length coding

System and method for employing a global bit for page sharing in a linear-addressed cache

Processing requests to efficiently access a limited bandwidth storage area

Method and system for dynamic resource allocation

Method and system for transforming memory location references in instructions

System and method for employing a global bit for page sharing in a linear-addressed cache

System and method for employing a process identifier to minimize aliasing in a linear-addressed cache

Decoupling the number of logical threads from the number of simultaneous physical threads in a processor

Decoupling request for ownership tag reads from data read operations

Apparatus and method for store address for store address prefetch and line locking

Late allocation of registers

Method for and a trailing store buffer for use in memory renaming