Inventor
GURRAM CHANDRA
US22 patents
Patents
22 patentsUS11361496B2Jun 14, 2022
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
INTEL CORP41 citations97
US12007935B2Jun 11, 2024
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
INTEL CORP11 citations94
US11709793B2Jul 25, 2023
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
INTEL CORP9 citations94
US11182337B1Nov 23, 2021
Computing efficient cross channel operations in parallel computing machines using systolic arrays
INTEL CORP9 citations85
US11954063B2Apr 9, 2024
Graphics processors and graphics processing units having dot product accumulate instruction for hybrid floating point format
INTEL CORP2 citations84
US11204977B2Dec 21, 2021
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
INTEL CORP7 citations83
US10983581B2Apr 20, 2021
Resource load balancing based on usage and power limits
INTEL CORP12 citations82
US11977885B2May 7, 2024
Utilizing structured sparsity in systolic arrays
INTEL CORP2 citations72
US11636174B2Apr 25, 2023
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
INTEL CORP3 citations72
US12346694B2Jul 1, 2025
Register file for systolic array
INTEL CORP1 citations63
US12189571B2Jan 7, 2025
Dual pipeline parallel systolic array
INTEL CORP1 citations63
US12174783B2Dec 24, 2024
Systolic array of arbitrary physical and logical depth
INTEL CORP0 citations62
US12093213B2Sep 17, 2024
Computing efficient cross channel operations in parallel computing machines using systolic arrays
INTEL CORP0 citations62
US12039001B2Jul 16, 2024
Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs
INTEL CORP0 citations62
US11669490B2Jun 6, 2023
Computing efficient cross channel operations in parallel computing machines using systolic arrays
INTEL CORP1 citations62
US11163578B2Nov 2, 2021
Systems and methods for reducing register bank conflicts based on a software hint bit causing a hardware thread switch
INTEL CORP1 citations62
US12405787B2Sep 2, 2025
Utilizing structured sparsity in systolic arrays
INTEL CORP0 citations61
US12386617B2Aug 12, 2025
Gathering payload from arbitrary registers for send messages in a graphics environment
INTEL CORP0 citations60
US12210905B2Jan 28, 2025
Multiple register allocation sizes for threads
INTEL CORP0 citations60
US12190158B2Jan 7, 2025
Using sparsity metadata to reduce systolic array power consumption
INTEL CORP0 citations51
US12399685B2Aug 26, 2025
Systolic array having support for output sparsity
INTEL CORP0 citations50
US10754651B2Aug 25, 2020
Register bank conflict reduction for multi-threaded processor
INTEL CORP0 citations41