Inventor
CHERN GEENG-CHUAN
US50 patents
⚠️ This page may combine multiple inventors who share the name “CHERN GEENG-CHUAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEFECHIP CORPORATION LTD
15 patentsUS11217744B2Jan 4, 2022
Magnetic memory device with multiple sidewall spacers covering sidewall of MTJ element and method for manufacturing the same
HEFECHIP CORPORATION LTD7 citations86
US11315937B2Apr 26, 2022
1.5-transistor (1.5T) one time programmable (OTP) memory with thin gate to drain dielectric and methods thereof
HEFECHIP CORPORATION LTD3 citations73
US11177431B2Nov 16, 2021
Magnetic memory device and method for manufacturing the same
HEFECHIP CORPORATION LTD2 citations73
US11139368B2Oct 5, 2021
Trench capacitor having improved capacitance and fabrication method thereof
HEFECHIP CORPORATION LTD3 citations73
US11114140B1Sep 7, 2021
One time programmable (OTP) bits for physically unclonable functions
HEFECHIP CORPORATION LTD5 citations73
US11074985B1Jul 27, 2021
One-time programmable memory device and method for operating the same
HEFECHIP CORPORATION LTD2 citations73
US11776992B2Oct 3, 2023
Trench capacitor having improved capacitance and fabrication method thereof
HEFECHIP CORPORATION LTD0 citations62
US11610893B2Mar 21, 2023
Method for fabricating semiconductor memory device with buried capacitor and fin-like electrodes
HEFECHIP CORPORATION LTD0 citations62
US11545617B2Jan 3, 2023
Method of fabricating magnetic memory device
HEFECHIP CORPORATION LTD0 citations62
US11362097B1Jun 14, 2022
One-time programmable memory device and fabrication method thereof
HEFECHIP CORPORATION LTD1 citations62
US11296090B2Apr 5, 2022
Semiconductor memory device with buried capacitor and fin-like electrodes
HEFECHIP CORPORATION LTD1 citations62
US11152381B1Oct 19, 2021
MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same
HEFECHIP CORPORATION LTD1 citations62
US11437082B2Sep 6, 2022
Physically unclonable function circuit having lower gate-to-source/drain breakdown voltage
HEFECHIP CORPORATION LTD0 citations52
US11322500B2May 3, 2022
Stacked capacitor with horizontal and vertical fin structures and method for making the same
HEFECHIP CORPORATION LTD0 citations52
US11114442B2Sep 7, 2021
Semiconductor memory device with shallow buried capacitor and fabrication method thereof
HEFECHIP CORPORATION LTD0 citations52
APD SEMICONDUCTOR INC
9 patentsUS6448160B1Sep 10, 2002
Method of fabricating power rectifier device to vary operating parameters and resulting device
APD SEMICONDUCTOR INC99 citations98
US6399996B1Jun 4, 2002
Schottky diode having increased active surface area and method of fabrication
APD SEMICONDUCTOR INC99 citations98
US6420225B1Jul 16, 2002
Method of fabricating power rectifier device
APD SEMICONDUCTOR INC86 citations97
US6426541B2Jul 30, 2002
Schottky diode having increased forward current with improved reverse bias characteristics and method of fabrication
APD SEMICONDUCTOR INC55 citations96
US6404033B1Jun 11, 2002
Schottky diode having increased active surface area with improved reverse bias characteristics and method of fabrication
APD SEMICONDUCTOR INC68 citations96
US6743703B2Jun 1, 2004
Power diode having improved on resistance and breakdown voltage
APD SEMICONDUCTOR INC74 citations95
US6515330B1Feb 4, 2003
Power device having vertical current path with enhanced pinch-off for current limiting
APD SEMICONDUCTOR INC40 citations92
US6979861B2Dec 27, 2005
Power device having reduced reverse bias leakage current
APD SEMICONDUCTOR INC25 citations91
US6537860B2Mar 25, 2003
Method of fabricating power VLSI diode devices
APD SEMICONDUCTOR INC19 citations82
ATMEL CORP
8 patentsUS5081054AJan 14, 1992
Fabrication process for programmable and erasable MOS memory device
ATMEL CORP88 citations96
US5066992ANov 19, 1991
Programmable and erasable MOS memory device
ATMEL CORP58 citations96
US4859619AAug 22, 1989
EPROM fabrication process forming tub regions for high voltage devices
ATMEL CORP70 citations95
US4833096AMay 23, 1989
EEPROM fabrication process
ATMEL CORP80 citations94
USRE35094ENov 21, 1995
Fabrication process for programmable and erasable MOS memory device
ATMEL CORP14 citations73
US9502581B2Nov 22, 2016
Non-volatile floating gate memory cells
ATMEL CORP2 citations63
US9595335B2Mar 14, 2017
Memory device and systems and methods for selecting memory cells in the memory device
ATMEL CORP0 citations48
US9142306B2Sep 22, 2015
Selecting memory cells using source lines
ATMEL CORP1 citations48
NEXCHIP SEMICONDUCTOR CO LTD
6 patentsUS11088155B2Aug 10, 2021
Method for fabricating split-gate non-volatile memory
NEXCHIP SEMICONDUCTOR CO LTD0 citations62
US10916664B2Feb 9, 2021
Non-volatile memory and manufacturing method for the same
NEXCHIP SEMICONDUCTOR CO LTD1 citations62
US11049947B2Jun 29, 2021
Non-volatile memory and manufacturing method for the same
NEXCHIP SEMICONDUCTOR CO LTD0 citations51
US10854758B2Dec 1, 2020
Non-volatile memory and manufacturing method for the same
NEXCHIP SEMICONDUCTOR CO LTD0 citations51
US10726894B2Jul 28, 2020
Non-volatile memory cell, array and fabrication method
NEXCHIP SEMICONDUCTOR CO LTD0 citations51
US10636801B2Apr 28, 2020
Split-gate non-volatile memory and fabrication method thereof
NEXCHIP SEMICONDUCTOR CO LTD0 citations51
SILICON STORAGE TECH INC
5 patentsUS6563167B2May 13, 2003
Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges
SILICON STORAGE TECH INC34 citations92
US7084453B2Aug 1, 2006
Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric
SILICON STORAGE TECH INC7 citations74
US6967372B2Nov 22, 2005
Semiconductor memory array of floating gate memory cells with vertical control gate sidewalls and insulation spacers
SILICON STORAGE TECH INC8 citations74
US7008846B2Mar 7, 2006
Non-volatile floating gate memory cell with floating gates formed as spacers, and an array thereof, and a method of manufacturing
SILICON STORAGE TECH INC2 citations63
US6750090B2Jun 15, 2004
Self aligned method of forming a semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges, and a memory array made thereby
SILICON STORAGE TECH INC2 citations63
NEXCHIP SEMICONDUCTOR CORP
3 patentsUS10971595B2Apr 6, 2021
MOFSET and method of fabricating same
NEXCHIP SEMICONDUCTOR CORP0 citations62
US10957776B2Mar 23, 2021
Method of fabricating MOSFET
NEXCHIP SEMICONDUCTOR CORP0 citations62
US10950601B2Mar 16, 2021
Current source using emitter region as base region isolation structure
NEXCHIP SEMICONDUCTOR CORP0 citations52