Inventor
URATANI MUNEHIRO
JP9 patents
Patents
9 patentsUS5353251AOct 4, 1994
Memory cell circuit with single bit line latch
SHARP KK57 citations94
US4783692ANov 8, 1988
CMOS gate array
SHARP KK31 citations91
US4684829AAug 4, 1987
CMOS tree decoder with speed enhancement by adjustment of gate width
SHARP KK35 citations91
US5610850AMar 11, 1997
Absolute difference accumulator circuit
SHARP KK41 citations90
US7447289B2Nov 4, 2008
Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
SHARP KK10 citations84
US7529528B2May 5, 2009
Power consumption controlling apparatus for high frequency amplifier
SHARP KK7 citations73
US7248095B2Jul 24, 2007
Bus driver with well voltage control section
SHARP KK3 citations62
US6546542B2Apr 8, 2003
Parameterized designing method of data driven information processor employing self-timed pipeline control
SHARP KK6 citations62
US4453236AJun 5, 1984
Memory array addressing circuitry
SHARP KK5 citations62