Inventor
MATHEW RANJAN J
US30 patents
⚠️ This page may combine multiple inventors who share the name “MATHEW RANJAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NAT SEMICONDUCTOR CORP
27 patentsUS5804880ASep 8, 1998
Solder isolating lead frame
NAT SEMICONDUCTOR CORP105 citations98
US5596225AJan 21, 1997
Leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die
NAT SEMICONDUCTOR CORP55 citations96
US5328079AJul 12, 1994
Method of and arrangement for bond wire connecting together certain integrated circuit components
NAT SEMICONDUCTOR CORP148 citations96
US4922322AMay 1, 1990
Bump structure for reflow bonding of IC devices
NAT SEMICONDUCTOR CORP61 citations96
US5923995AJul 13, 1999
Methods and apparatuses for singulation of microelectromechanical systems
NAT SEMICONDUCTOR CORP258 citations95
US6384890B1May 7, 2002
Connection assembly for reflective liquid crystal projection with branched PCB display
NAT SEMICONDUCTOR CORP25 citations93
US6122033ASep 19, 2000
Fusible seal for LCD devices and methods for making same
NAT SEMICONDUCTOR CORP43 citations93
US6476885B1Nov 5, 2002
Stress-free socketed optical display package with die non-rigidly attached to containment structure
NAT SEMICONDUCTOR CORP56 citations92
US6357763B2Mar 19, 2002
Seal for LCD devices and methods for making same
NAT SEMICONDUCTOR CORP33 citations92
US6284566B1Sep 4, 2001
Chip scale package and method for manufacture thereof
NAT SEMICONDUCTOR CORP20 citations92
US5728285AMar 17, 1998
Protective coating combination for lead frames
NAT SEMICONDUCTOR CORP41 citations92
US5650661AJul 22, 1997
Protective coating combination for lead frames
NAT SEMICONDUCTOR CORP34 citations92
US5436082AJul 25, 1995
Protective coating combination for lead frames
NAT SEMICONDUCTOR CORP33 citations92
US5208186AMay 4, 1993
Process for reflow bonding of bumps in IC devices
NAT SEMICONDUCTOR CORP37 citations92
US6356334B1Mar 12, 2002
Liquid crystal display assembly and method for reducing residual stresses
NAT SEMICONDUCTOR CORP45 citations91
US6054338AApr 25, 2000
Low cost ball grid array device and method of manufacture thereof
NAT SEMICONDUCTOR CORP26 citations91
US5783866AJul 21, 1998
Low cost ball grid array device and method of manufacture thereof
NAT SEMICONDUCTOR CORP32 citations91
US5270262ADec 14, 1993
O-ring package
NAT SEMICONDUCTOR CORP35 citations91
US4800178AJan 24, 1989
Method of electroplating a copper lead frame with copper
NAT SEMICONDUCTOR CORP25 citations86
US6556269B1Apr 29, 2003
Connection assembly for reflective liquid crystal display and method
NAT SEMICONDUCTOR CORP13 citations84
US5969783AOct 19, 1999
Reflective liquid crystal display and connection assembly and method
NAT SEMICONDUCTOR CORP19 citations84
US6255141B1Jul 3, 2001
Method of packaging fuses
NAT SEMICONDUCTOR CORP6 citations74
US6140708AOct 31, 2000
Chip scale package and method for manufacture thereof
NAT SEMICONDUCTOR CORP13 citations74
US6498636B1Dec 24, 2002
Apparatus and method for substantially stress-free electrical connection to a liquid crystal display
NAT SEMICONDUCTOR CORP11 citations70
US7102703B1Sep 5, 2006
Liquid crystal display assembly for reducing optical defects
NAT SEMICONDUCTOR CORP10 citations69
US6459143B2Oct 1, 2002
Method of packaging fuses
NAT SEMICONDUCTOR CORP2 citations63
US4963233AOct 16, 1990
Glass conditioning for ceramic package plating
NAT SEMICONDUCTOR CORP2 citations63
INTEL CORP
3 patentsUS6927156B2Aug 9, 2005
Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
INTEL CORP62 citations96
US7880310B2Feb 1, 2011
Direct device attachment on dual-mode wirebond die
INTEL CORP36 citations92
US7262513B2Aug 28, 2007
Apparatus and method extending flip-chip pad structures for wirebonding on low-k dielectric silicon
INTEL CORP11 citations84