Inventor
LEWIS JERRY D
US12 patents
⚠️ This page may combine multiple inventors who share the name “LEWIS JERRY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
8 patentsUS5613153AMar 18, 1997
Coherency and synchronization mechanisms for I/O channel controllers in a data processing system
IBM96 citations96
US8024527B2Sep 20, 2011
Partial cache line accesses based on memory access patterns
IBM7 citations84
US7958309B2Jun 7, 2011
Dynamic selection of a memory access size
IBM12 citations84
US7779148B2Aug 17, 2010
Dynamic routing based on information of not responded active source requests quantity received in broadcast heartbeat signal and stored in local data structure for other processor chips
IBM15 citations84
US5548797AAug 20, 1996
Digital clock pulse positioning circuit for delaying a signal input by a fist time duration and a second time duration to provide a positioned clock signal
IBM10 citations73
US7827428B2Nov 2, 2010
System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
IBM4 citations63
US5623694AApr 22, 1997
Aborting an I/O operation started before all system data is received by the I/O controller after detecting a remote retry operation
IBM4 citations62
US7921316B2Apr 5, 2011
Cluster-wide system clock in a multi-tiered full-graph interconnect architecture
IBM0 citations52
ARIMILLI LAKSHMINARAYANA B
4 patentsUS8077602B2Dec 13, 2011
Performing dynamic request routing based on broadcast queue depths
ARIMILLI LAKSHMINARAYANA B23 citations92
US8108619B2Jan 31, 2012
Cache management for partial cache line operations
ARIMILLI LAKSHMINARAYANA B9 citations84
US8255635B2Aug 28, 2012
Claiming coherency ownership of a partial cache line of data
ARIMILLI LAKSHMINARAYANA B2 citations62
US8117401B2Feb 14, 2012
Interconnect operation indicating acceptability of partial data delivery
ARIMILLI LAKSHMINARAYANA B3 citations62