Inventor

YU CHING

US55 patents

⚠️ This page may combine multiple inventors who share the name “YU CHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU CHING

ADVANCED MICRO DEVICES INC

Method and apparatus in a network switch for handling link failure and link recovery in a trunked data path

Apparatus and method for remote wake-up in system having interlinked networks

Apparatus and method for modifying a limit of a retry counter in a network switch port in response to exerting backpressure

Method and apparatus for reclaiming buffers using a single buffer bit

Method and apparatus for allowing a remote node to awaken a sleeping node of a network

Apparatus and method in a network interface for enabling power up of a host computer using magic packet and on-now power up management schemes

Method and apparatus for operating a network switch in a CPU-less environment

Power management indication mechanism for supporting power saving mode in computer system

Using an index and count mechanism to coordinate access to a shared resource by interactive devices

Apparatus and method in a network switch for swapping memory access slots between gigabit port and expansion port

Apparatus and methods for storing and processing header information in a network switch

Address table overflow management in a network switch

Method and apparatus for interfacing between systems operating under different clock regimes with interlocking to prevent overwriting of data

Programming the size of a broad-specific boot ROM

Apparatus and method for programmable memory access slot assignment

Apparatus and method for resetting a retry counter in a network switch port in response to exerting backpressure

Apparatus and method for programmably modifying a limit of a retry counter in a network switch port in response to exerting backpressure

Bandwidth efficiency in cascaded scheme

Apparatus and method for storing header information in a network switch

Mechanism for accumulating data to determine average values of performance parameters

Apparatus and method in a network switch for dynamically assigning memory interface slots between gigabit port and expansion port

Freezing mechanism for debugging

Data communications device and associated method for arbitrating access using dynamically programmable arbitration scheme and limits on data transfers

System and method for programming late collision slot time

Apparatus and method for selectively controlling clocking and resetting of a network interface

Interrupt management system having batch mechanism for handling interrupt events

Generation of a stable reference clock frequency from a base clock frequency that may vary depending on source

Two-part memory address generator

Generic register interface for accessing registers located in different clock domains

Tracking availability of elements within a shared list of elements from an index and count mechanism

Network interface supporting fifo-type and SRAM-type accesses to internal buffer memory

Method and system for switching between a totem-pole drive mode and an open-drain drive mode

Multi-phase EEPROM reading for network interface initialization

Emulation of an m bit counter driven by a desired clock frequency given a central clock frequency

SOLARFLARE COMMUNICATIONS INC

Transmit completion event batching

Interrupt management for multiple event queues

Packet validation in virtual network interface architecture

Queue depth management for communication between host and peripheral device

Hashing algorithm for network receive filtering

Hashing algorithm for network receive filtering

Transmit rate pacing system and method

Packet validation in virtual network interface architecture

Packet validation in virtual network interface architecture

Including descriptor queue empty events in completion events

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device and manufacturing method thereof

Semiconductor device and manufacturing method thereof

LEVEL 5 NETWORKS INC

DMA descriptor queue read and cache write pointer arrangement

POPE STEVEN L

Interrupt management for multiple event queues

(unassigned)

Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer

XILINX INC

Packet validation in virtual network interface architecture