Inventor

MACLAREN JOHN M

US40 patents

⚠️ This page may combine multiple inventors who share the name “MACLAREN JOHN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MACLAREN JOHN M

HEWLETT PACKARD DEVELOPMENT CO

Memory latency and bandwidth optimizations

Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency

Memory latency and bandwidth optimizations

Method for supporting multi-level stripping of non-homogeneous memory to maximize concurrency

Memory sub-system error cleansing

Real-time hardware memory scrubbing

Hot-upgrade/hot-add memory

Hot-replace of memory

Hot-plug memory catridge power control logic

Raid memory

Removable memory cartridge system for use with a server or other processor-based device

Hot replace power control sequence logic

Removable memory cartridge system for use with a server or other processor-based device

Error indication in a raid memory system

Error indication in a raid memory system

Hard/soft error detection

Hot replace power control sequence logic

Memory auto-precharge

Technique for identifying multiple circuit components

Technique for identifying multiple circuit components

Removable memory cartridge system for use with a server or other processor-based device

Removable memory cartridge system for use with a server or other processor-based device

COMPAQ COMPUTER CORP

Fault tolerant computer system

Computer expansion slot and associated logic for automatically detecting compatibility with an expansion card

Fault tolerant computer system

Prefetching data in response to a read transaction for which the requesting device relinquishes control of the data bus while awaiting data requested in the transaction

Bridge circuit comprising independent transaction buffers with control logic adapted to store overflow data in second buffer when transaction size exceeds the first buffer size

Multi-threaded bus master

Providing data from a bridge to a requesting device while the bridge is receiving the data

CADENCE DESIGN SYSTEMS INC

System and method for memory control having address integrity protection for error-protected data words of memory transactions

Multi-channel memory interface

Caching error checking data for memory having inline storage configurations

Programmable, area-optimized bank group rotation system for memory devices

Memory command interleaving

Address failure detection for memory devices having inline storage configurations

COMPAQ INFORMATION TECHNOLOGIE

Architecture, system and method for ensuring an ordered transaction on at least one of a plurality of multi-processor buses that experience a hit-to-modified snoop cycle

Technique for identifying multiple circuit components

(unassigned)

Ordering transactions

Storing data associated with one request while continuing to store data associated with a previous request from the same device

HEWLETT PACKARD COMPANY L P

Memory data verify operation