Inventor

KAWASAKI IKUYA

JP43 patents

⚠️ This page may combine multiple inventors who share the name “KAWASAKI IKUYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAWASAKI IKUYA

HITACHI LTD

Processor with an addressable address translation buffer operative in associative and non-associative modes

Data processor having an address translation buffer operable with variable page sizes

Data processor and single-chip microcomputer with changing clock frequency and operating voltage

Microprocessor operating at high and low clok frequencies

Data processor for implementing virtual pages using a cache and register

Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler

Translation lookaside buffer supporting multiple page sizes

Microprocessor having PC card interface

Data processing system with coprocessor

Information processing apparatus

Accessing exception handlers without translating the address

Microprocessor for inserting a bus cycle in an instruction set to output an internal information for an emulation

System for logical address conversion data fetching from external storage and indication signal for indicating the information externally

Software debugging system for writing a logical address conversion data into a trace memory of an emulator

Data processing system

Microprocessor having a PC card type interface

Microprocessor system

Microprocessor for retrying data transfer

Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit

Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system

Data processor

Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses

Data processing system having a card type interface with assigned addressing

Data processing system having a PC card type interface with assigned addressing

Data processor

Purge control for ON-chip cache memory

Data processor having logical address memories and purge capabilities

Microprocessor having ability to carry out logical operation on internal bus

Data processing system

Data processor with on-chip logical addressing and off-chip physical addressing

Data processing system

Method of searching a queue in response to a search instruction

Information storage system, information transfer system and storage medium thereof

Data processor capable of executing an instruction that makes a cache memory ineffective

Data processor with on-chip cache memory and purge controller responsive to external signal for controlling access to the cache memory

Method of searching a queue in response to a search instruction

SAKAMURA KEN

Data processing system having apparatus for increasing the execution speed of bit field instructions

Data processing system having apparatus for increasing the execution speed of bit field instructions

Method of searching a queue in response to a search instruction

Microprocessor having apparatus for dynamically controlling a kind of operation to be performed by instructions to be executed

RENESAS TECH CORP

Information processing apparatus having a bus using the protocol of the acknowledge type in the source clock synchronous system

Semiconductor device

HITACHI MICROCUMPUTER ENG

System using microprocessor address lines for coprocessor selection within a multi-coprocessor apparatus