Inventor
STUECHELI JEFFREY ADAM
US27 patents
⚠️ This page may combine multiple inventors who share the name “STUECHELI JEFFREY ADAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS7469318B2Dec 23, 2008
System bus structure for large L2 cache array topology with different latency domains
IBM46 citations96
US7584329B2Sep 1, 2009
Data processing system and method for efficient communication utilizing an Ig coherency state
IBM36 citations93
US7543120B2Jun 2, 2009
Processor and data processing system employing a variable store gather window
IBM19 citations93
US7366851B2Apr 29, 2008
Processor, method, and data processing system employing a variable store gather window
IBM25 citations93
US7467323B2Dec 16, 2008
Data processing system and method for efficient storage of metadata in a system memory
IBM33 citations92
US8352712B2Jan 8, 2013
Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted
IBM33 citations90
US7401189B2Jul 15, 2008
Pipelining D states for MRU steerage during MRU/LRU member allocation
IBM9 citations84
US7058767B2Jun 6, 2006
Adaptive memory access speculation
IBM15 citations84
US7380066B2May 27, 2008
Store stream prefetching in a microprocessor
IBM13 citations83
US7779292B2Aug 17, 2010
Efficient storage of metadata in a system memory
IBM7 citations74
US7774555B2Aug 10, 2010
Data processing system and method for efficient coherency communication utilizing coherency domain indicators
IBM5 citations74
US7363433B2Apr 22, 2008
Cache member protection with partial make MRU allocation
IBM5 citations74
US7103721B2Sep 5, 2006
Cache allocation mechanism for biasing subsequent allocations based upon cache directory state
IBM7 citations74
US6493814B2Dec 10, 2002
Reducing resource collisions associated with memory units in a multi-level hierarchy memory system
IBM8 citations74
US8015358B2Sep 6, 2011
System bus structure for large L2 cache array topology with different latency domains
IBM1 citations63
US7783841B2Aug 24, 2010
Efficient coherency communication utilizing an IG coherency state
IBM4 citations63
US7689777B2Mar 30, 2010
Cache member protection with partial make MRU allocation
IBM2 citations63
US7568076B2Jul 28, 2009
Variable store gather window
IBM2 citations63
US6965852B2Nov 15, 2005
Pseudo random test pattern generation using Markov chains
IBM4 citations63
US7716427B2May 11, 2010
Store stream prefetching in a microprocessor
IBM2 citations62
US7600091B2Oct 6, 2009
Executing background writes to idle DIMMS
IBM3 citations61
US7516264B2Apr 7, 2009
Programmable bank/timer address folding in memory devices
IBM5 citations61
US7373471B2May 13, 2008
Executing background writes to idle DIMMs
IBM4 citations61
US7840758B2Nov 23, 2010
Variable store gather window
IBM0 citations52
US7793048B2Sep 7, 2010
System bus structure for large L2 cache array topology with different latency domains
IBM0 citations52
FIELDS JR JAMES STEPHEN
2 patentsUS8214600B2Jul 3, 2012
Data processing system and method for efficient coherency communication utilizing coherency domains
FIELDS JR JAMES STEPHEN3 citations61
US8230178B2Jul 24, 2012
Data processing system and method for efficient coherency communication utilizing coherency domain indicators
FIELDS JR JAMES STEPHEN0 citations51