Inventor
CHOU CHIU-MING
TW53 patents
⚠️ This page may combine multiple inventors who share the name “CHOU CHIU-MING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MEGICA CORP
32 patentsUS7465654B2Dec 16, 2008
Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
MEGICA CORP60 citations98
US7372161B2May 13, 2008
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP58 citations98
US7271489B2Sep 18, 2007
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP69 citations98
US8004092B2Aug 23, 2011
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP42 citations96
US7423346B2Sep 9, 2008
Post passivation interconnection process and structures
MEGICA CORP48 citations96
US7397121B2Jul 8, 2008
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP49 citations96
US8022544B2Sep 20, 2011
Chip structure
MEGICA CORP17 citations93
US7960269B2Jun 14, 2011
Method for forming a double embossing structure
MEGICA CORP21 citations93
US7582966B2Sep 1, 2009
Semiconductor chip and method for fabricating the same
MEGICA CORP35 citations93
US7452803B2Nov 18, 2008
Method for fabricating chip structure
MEGICA CORP20 citations93
US7416971B2Aug 26, 2008
Top layers of metal for integrated circuits
MEGICA CORP36 citations93
US7381642B2Jun 3, 2008
Top layers of metal for integrated circuits
MEGICA CORP29 citations93
US7355282B2Apr 8, 2008
Post passivation interconnection process and structures
MEGICA CORP31 citations93
US8362588B2Jan 29, 2013
Semiconductor chip with coil element over passivation layer
MEGICA CORP14 citations92
US7547969B2Jun 16, 2009
Semiconductor chip with passivation layer comprising metal interconnect and contact pads
MEGICA CORP22 citations92
US7470927B2Dec 30, 2008
Semiconductor chip with coil element over passivation layer
MEGICA CORP30 citations92
US7947978B2May 24, 2011
Semiconductor chip with bond area
MEGICA CORP27 citations91
US7855461B2Dec 21, 2010
Chip structure with bumps and testing pads
MEGICA CORP19 citations91
US7394161B2Jul 1, 2008
Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto
MEGICA CORP24 citations91
US7985653B2Jul 26, 2011
Semiconductor chip with coil element over passivation layer
MEGICA CORP8 citations84
US7973401B2Jul 5, 2011
Stacked chip package with redistribution lines
MEGICA CORP8 citations84
US7964973B2Jun 21, 2011
Chip structure
MEGICA CORP8 citations84
US7508059B2Mar 24, 2009
Stacked chip package with redistribution lines
MEGICA CORP12 citations84
US7482268B2Jan 27, 2009
Top layers of metal for integrated circuits
MEGICA CORP9 citations84
US7521805B2Apr 21, 2009
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP7 citations74
US7462558B2Dec 9, 2008
Method for fabricating a circuit component
MEGICA CORP7 citations74
US8344524B2Jan 1, 2013
Wire bonding method for preventing polymer cracking
MEGICA CORP2 citations63
US8018060B2Sep 13, 2011
Post passivation interconnection process and structures
MEGICA CORP4 citations63
US8013449B2Sep 6, 2011
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP4 citations63
US8008775B2Aug 30, 2011
Post passivation interconnection structures
MEGICA CORP5 citations63
US7592205B2Sep 22, 2009
Over-passivation process of forming polymer layer over IC chip
MEGICA CORP4 citations63
US7417317B2Aug 26, 2008
Post passivation interconnection schemes on top of the IC chips
MEGICA CORP4 citations63
LIN MOU-SHIUNG
11 patentsUS8399989B2Mar 19, 2013
Metal pad or metal bump over pad exposed by passivation layer
LIN MOU-SHIUNG20 citations92
US8552559B2Oct 8, 2013
Very thick metal interconnection scheme in IC chips
LIN MOU-SHIUNG9 citations84
US8426958B2Apr 23, 2013
Stacked chip package with redistribution lines
LIN MOU-SHIUNG5 citations84
US8319354B2Nov 27, 2012
Semiconductor chip with post-passivation scheme formed over passivation layer
LIN MOU-SHIUNG8 citations84
US8304907B2Nov 6, 2012
Top layers of metal for integrated circuits
LIN MOU-SHIUNG8 citations84
US8148822B2Apr 3, 2012
Bonding pad on IC substrate and method for making the same
LIN MOU-SHIUNG12 citations84
US8304766B2Nov 6, 2012
Semiconductor chip with a bonding pad having contact and test areas
LIN MOU-SHIUNG5 citations72
US8519552B2Aug 27, 2013
Chip structure
LIN MOU-SHIUNG3 citations63
US8168527B2May 1, 2012
Semiconductor chip and method for fabricating the same
LIN MOU-SHIUNG3 citations63
US8159074B2Apr 17, 2012
Chip structure
LIN MOU-SHIUNG3 citations63
US8120181B2Feb 21, 2012
Post passivation interconnection process and structures
LIN MOU-SHIUNG3 citations63
CHOU CHIU-MING
4 patentsUS8592977B2Nov 26, 2013
Integrated circuit (IC) chip and method for fabricating the same
CHOU CHIU-MING11 citations83
US8581404B2Nov 12, 2013
Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures
CHOU CHIU-MING7 citations83
US8242601B2Aug 14, 2012
Semiconductor chip with passivation layer comprising metal interconnect and contact pads
CHOU CHIU-MING7 citations83
US8198729B2Jun 12, 2012
Connection between a semiconductor chip and a circuit component with a large contact area
CHOU CHIU-MING7 citations83
CHOU CHIEN-KANG
2 patentsICOMETRUE CO LTD
1 patentShowing the top 50 of 53 patents by PatentIndex Score.