Inventor
LO HSIN-JUNG
TW31 patents
⚠️ This page may combine multiple inventors who share the name “LO HSIN-JUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MEGICA CORP
18 patentsUS8004092B2Aug 23, 2011
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP42 citations96
US7397121B2Jul 8, 2008
Semiconductor chip with post-passivation scheme formed over passivation layer
MEGICA CORP49 citations96
US7960269B2Jun 14, 2011
Method for forming a double embossing structure
MEGICA CORP21 citations93
US7473999B2Jan 6, 2009
Semiconductor chip and process for forming the same
MEGICA CORP40 citations93
US7452803B2Nov 18, 2008
Method for fabricating chip structure
MEGICA CORP20 citations93
US7947978B2May 24, 2011
Semiconductor chip with bond area
MEGICA CORP27 citations91
US8368193B2Feb 5, 2013
Chip package
MEGICA CORP6 citations84
US8044475B2Oct 25, 2011
Chip package
MEGICA CORP11 citations84
US7973401B2Jul 5, 2011
Stacked chip package with redistribution lines
MEGICA CORP8 citations84
US7964973B2Jun 21, 2011
Chip structure
MEGICA CORP8 citations84
US7964961B2Jun 21, 2011
Chip package
MEGICA CORP16 citations84
US7508059B2Mar 24, 2009
Stacked chip package with redistribution lines
MEGICA CORP12 citations84
US9612615B2Apr 4, 2017
Integrated circuit chip using top post-passivation technology and bottom structure technology
MEGICA CORP15 citations83
US7990037B2Aug 2, 2011
Carbon nanotube circuit component structure
MEGICA CORP6 citations74
US7495304B2Feb 24, 2009
Chip package
MEGICA CORP7 citations74
US7462558B2Dec 9, 2008
Method for fabricating a circuit component
MEGICA CORP7 citations74
US8344524B2Jan 1, 2013
Wire bonding method for preventing polymer cracking
MEGICA CORP2 citations63
US7932172B2Apr 26, 2011
Semiconductor chip and process for forming the same
MEGICA CORP0 citations52
LIN MOU-SHIUNG
9 patentsUS8456856B2Jun 4, 2013
Integrated circuit chip using top post-passivation technology and bottom structure technology
LIN MOU-SHIUNG138 citations98
US8399989B2Mar 19, 2013
Metal pad or metal bump over pad exposed by passivation layer
LIN MOU-SHIUNG20 citations92
US8426958B2Apr 23, 2013
Stacked chip package with redistribution lines
LIN MOU-SHIUNG5 citations84
US8319354B2Nov 27, 2012
Semiconductor chip with post-passivation scheme formed over passivation layer
LIN MOU-SHIUNG8 citations84
US8232192B2Jul 31, 2012
Process of bonding circuitry components
LIN MOU-SHIUNG8 citations84
US8148822B2Apr 3, 2012
Bonding pad on IC substrate and method for making the same
LIN MOU-SHIUNG12 citations84
US8304766B2Nov 6, 2012
Semiconductor chip with a bonding pad having contact and test areas
LIN MOU-SHIUNG5 citations72
US8159074B2Apr 17, 2012
Chip structure
LIN MOU-SHIUNG3 citations63
US8692374B2Apr 8, 2014
Carbon nanotube circuit component structure
LIN MOU-SHIUNG0 citations52