Inventor
CHOUBAL ASHISH V
US28 patents
⚠️ This page may combine multiple inventors who share the name “CHOUBAL ASHISH V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
23 patentsUS9823719B2Nov 21, 2017
Controlling power delivery to a processor via a bypass
INTEL CORP11 citations92
US7165144B2Jan 16, 2007
Managing input/output (I/O) requests in a cache memory system
INTEL CORP43 citations89
US9910470B2Mar 6, 2018
Controlling telemetry data communication in a processor
INTEL CORP10 citations84
US7580406B2Aug 25, 2009
Remote direct memory access segment generation by a network controller
INTEL CORP17 citations84
US10429913B2Oct 1, 2019
Controlling power delivery to a processor via a bypass
INTEL CORP4 citations83
US10409346B2Sep 10, 2019
Controlling power delivery to a processor via a bypass
INTEL CORP4 citations83
US10146283B2Dec 4, 2018
Controlling power delivery to a processor via a bypass
INTEL CORP4 citations83
US9710041B2Jul 18, 2017
Masking a power state of a core of a processor
INTEL CORP7 citations83
US7761529B2Jul 20, 2010
Method, system, and program for managing memory requests by devices
INTEL CORP17 citations78
US10613611B2Apr 7, 2020
Current control for a multicore processor
INTEL CORP1 citations73
US11157052B2Oct 26, 2021
Controlling power delivery to a processor via a bypass
INTEL CORP2 citations72
US9727345B2Aug 8, 2017
Method for booting a heterogeneous system and presenting a symmetric core view
INTEL CORP3 citations72
US9335813B2May 10, 2016
Method and system for run-time reallocation of leakage current and dynamic power supply current
INTEL CORP5 citations72
US9665153B2May 30, 2017
Selecting a low power state based on cache flush latency determination
INTEL CORP2 citations71
US12314114B2May 27, 2025
Current control for a multicore processor
INTEL CORP0 citations62
US11762449B2Sep 19, 2023
Current control for a multicore processor
INTEL CORP0 citations62
US11237615B2Feb 1, 2022
Current control for a multicore processor
INTEL CORP0 citations62
US8352770B2Jan 8, 2013
Method, system and apparatus for low-power storage of processor context information
INTEL CORP3 citations62
US7562158B2Jul 14, 2009
Message context based TCP transmission
INTEL CORP4 citations62
US10963038B2Mar 30, 2021
Selecting a low power state based on cache flush latency determination
INTEL CORP0 citations60
US8719612B2May 6, 2014
Method, system and apparatus for low-power storage of processor context information
INTEL CORP0 citations51
US10503517B2Dec 10, 2019
Method for booting a heterogeneous system and presenting a symmetric core view
INTEL CORP0 citations50
US10198065B2Feb 5, 2019
Selecting a low power state based on cache flush latency determination
INTEL CORP0 citations50