Inventor
KUTTANNA BELLIAPPA M
US13 patents
⚠️ This page may combine multiple inventors who share the name “KUTTANNA BELLIAPPA M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
SUN MICROSYSTEMS INC
5 patentsUS6073212AJun 6, 2000
Reducing bandwidth and areas needed for non-inclusive memory hierarchy by using dual tags
SUN MICROSYSTEMS INC55 citations95
US5909697AJun 1, 1999
Reducing cache misses by snarfing writebacks in non-inclusive memory systems
SUN MICROSYSTEMS INC28 citations92
US6389517B1May 14, 2002
Maintaining snoop traffic throughput in presence of an atomic operation a first port for a first queue tracks cache requests and a second port for a second queue snoops that have yet to be filtered
SUN MICROSYSTEMS INC45 citations90
US6347360B1Feb 12, 2002
Apparatus and method for preventing cache data eviction during an atomic operation
SUN MICROSYSTEMS INC39 citations90
US6526485B1Feb 25, 2003
Apparatus and method for bad address handling
SUN MICROSYSTEMS INC11 citations72
INTEL CORP
4 patentsUS9164764B2Oct 20, 2015
Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode
INTEL CORP3 citations62
US8352770B2Jan 8, 2013
Method, system and apparatus for low-power storage of processor context information
INTEL CORP3 citations62
US9600283B2Mar 21, 2017
Single instruction for specifying a subset of registers to save prior to entering low-power mode, and for specifying a pointer to a function executed after exiting low-power mode
INTEL CORP0 citations51
US8719612B2May 6, 2014
Method, system and apparatus for low-power storage of processor context information
INTEL CORP0 citations51