Inventor

CALVIGNAC JEAN L

US61 patents

⚠️ This page may combine multiple inventors who share the name “CALVIGNAC JEAN L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CALVIGNAC JEAN L

IBM

Apparatus, method and program product to generate and use CRC in communications network

Longest prefix match lookup using hash function

Method and system for oversubscribing bandwidth in a communications network

Accessing an effective address and determining whether the effective address is associated with remotely coupled I/O adapters

DRAM access command queuing structure

Longest prefix match lookup using hash function

Merging of data cells in an ATM network

Statistical packet discard

DRAM access command queuing

Receive queue device with efficient queue flow control, segment placement and virtualization mechanisms

Multicore communication processing

Frame alteration logic for network processors

Apparatus and method for efficiently sharing memory bandwidth in a network processor

Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms

Transformation of bi-directional packet flow

Multi-bit Patricia trees

Method of inserting and deleting leaves in tree table structures

Non-coded information and companion data switching mechanism

Communication line adapter for use with a communications controller

Full virtualization of resources across an IP interconnect using page frame table

Split socket send queue apparatus and method with efficient queue flow control, retransmission and sack support mechanisms

Structure for scheduler pipeline design for hierarchical link sharing

Method and structure for enqueuing data packets for processing

Method for prevention of out-of-order delivery of data packets

Flexible network processor scheduler and data flow

Method and system for flexible network processor scheduler and data flow

Method and structure for deleting leaves in tree table structures

Frame alteration logic for network processors

Merging result from a parser in a network processor with result from an external coprocessor

Scheduler pipeline design for hierarchical link sharing

Flexible control block format for frame description and management

BASSO CLAUDE

Dual scheduling of work from multiple sources to multiple sinks using source and sink attributes to achieve fairness and processing efficiency

Bidirectional packet flow transformation

Host ethernet adapter for handling both endpoint and network node communications

Assignment constraint matrix for assigning work from multiple sources to multiple sinks

Deleting leaves in tree table structures

Merging result from a parser in a network processor with result from an external coprocessor

Assigning work from multiple sources to multiple sinks given assignment constraints

ABEL FRANCOIS

Selection of receive-queue based on packet attributes

Accelerating data packet parsing

Checksum verification accelerator

Identification of QoS classification based on packet attributes

Accelerating data packet parsing

Checksum verification accelerator

ALLEN JR JAMES J

Generation and use of CRC in communications network

Generation and use of CRC in communications network

ARIMILLI LAKSHMINARAYANA BABA

Techniques for dynamically assigning jobs to processors in a cluster based on broadcast information

Techniques for dynamically assigning jobs to processors in a cluster based on processor workload

ARIMILLI RAVI K

Supporting multiple high bandwidth I/O controllers on a single chip

CALVIGNAC JEAN L

Hash collision reduction system