Inventor
GORMAN KEVIN W
US44 patents
⚠️ This page may combine multiple inventors who share the name “GORMAN KEVIN W”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
31 patentsUS7458000B2Nov 25, 2008
Automatic shutdown or throttling of a bist state machine using thermal feedback
IBM20 citations92
US7444564B2Oct 28, 2008
Automatic bit fail mapping for embedded memories with clock multipliers
IBM23 citations90
US7870454B2Jan 11, 2011
Structure for system for and method of performing high speed memory diagnostics via built-in-self-test
IBM9 citations84
US7607060B2Oct 20, 2009
System and method for performing high speed memory diagnostics via built-in-self-test
IBM13 citations84
US6882583B2Apr 19, 2005
Method and apparatus for implementing DRAM redundancy fuse latches using SRAM
IBM16 citations84
US8914688B2Dec 16, 2014
System and method of reducing test time via address aware BIST circuitry
IBM8 citations80
US7631236B2Dec 8, 2009
Hybrid built-in self test (BIST) architecture for embedded memory arrays and an associated method
IBM9 citations77
US9734920B2Aug 15, 2017
Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories
IBM2 citations73
US8853847B2Oct 7, 2014
Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks
IBM5 citations73
US7194670B2Mar 20, 2007
Command multiplier for built-in-self-test
IBM9 citations73
US8935586B2Jan 13, 2015
Staggered start of BIST controllers and BIST engines
IBM6 citations69
US7917806B2Mar 29, 2011
System and method for indicating status of an on-chip power supply system
IBM3 citations63
US7702975B2Apr 20, 2010
Integration of LBIST into array BISR flow
IBM3 citations63
US6956415B2Oct 18, 2005
Modular DLL architecture for generating multiple timings
IBM2 citations63
US9460811B2Oct 4, 2016
Read only memory (ROM) with redundancy
IBM2 citations62
US7689887B2Mar 30, 2010
Automatic shutdown or throttling of a BIST state machine using thermal feedback
IBM4 citations62
US8612813B2Dec 17, 2013
Circuit and method for efficient memory repair
IBM3 citations61
US8381052B2Feb 19, 2013
Circuit and method for efficient memory repair
IBM2 citations61
US8028195B2Sep 27, 2011
Structure for indicating status of an on-chip power supply system
IBM5 citations61
US7757141B2Jul 13, 2010
Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry
IBM3 citations61
US7401281B2Jul 15, 2008
Remote BIST high speed test and redundancy calculation
IBM2 citations60
US7702976B2Apr 20, 2010
Integration of LBIST into array BISR flow
IBM2 citations54
US9224503B2Dec 29, 2015
Memory test with in-line error correction code logic
IBM0 citations52
US7937632B2May 3, 2011
Design structure and apparatus for a robust embedded interface
IBM0 citations52
US7565585B2Jul 21, 2009
Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system
IBM1 citations52
US10622090B2Apr 14, 2020
Arbitration for memory diagnostics
IBM0 citations51
US10153055B2Dec 11, 2018
Arbitration for memory diagnostics
IBM0 citations51
US9172373B2Oct 27, 2015
Verifying partial good voltage island structures
IBM1 citations51
US7472325B2Dec 30, 2008
Method for segmenting BIST functionality in an embedded memory array into remote lower-speed executable instructions and local higher-speed executable instructions
IBM1 citations50
US9773570B2Sep 26, 2017
Built-in-self-test (BIST) test time reduction
IBM0 citations41
US9514844B2Dec 6, 2016
Fast auto shift of failing memory diagnostics data using pattern detection
IBM0 citations40