Inventor

CASKEY TERRENCE

US37 patents

⚠️ This page may combine multiple inventors who share the name “CASKEY TERRENCE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CASKEY TERRENCE

INVENSAS CORP

Structure for microelectronic packaging with bond elements to encapsulation surface

BVA interposer

Structure for microelectronic packaging with bond elements to encapsulation surface

Reduced stress TSV and interposer structures

Reduced stress TSV and interposer structures

BVA interposer

Metal PVD-free conducting structures

Low CTE interposer without TSV structure

Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Method and structures for heat dissipating interposers

Method of fabricating low CTE interposer without TSV structure

Method for fabricating a carrier-less silicon interposer

Reliable device assembly

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Thin wafer handling and known good die test method

Method of fabricating low CTE interposer without TSV structure

Method of forming a reliable microelectronic assembly

Metal PVD-free conducting structures

Methods and structure for carrier-less thin wafer handling

Carrier-less silicon interposer

Methods and structure for carrier-less thin wafer handling

Method and structures for heat dissipating interposers

Method and structures for heat dissipating interposers

Structures for heat dissipating interposers

MCELREA SIMON J S

Electrically interconnected stacked die assemblies

Electrically interconnected stacked die assemblies

Wafer level surface passivation of stackable integrated circuit chips

UZOH CYPRIAN EMEKA

Reduced stress TSV and interposer structures

High strength through-substrate vias

WOYCHIK CHARLES G

Low-stress TSV design using conductive particles

Thin wafer handling and known good die test method

CASKEY TERRENCE

Microelectronic package with stacked microelectronic units and method for manufacture thereof

Vertical electrical interconnect formed on support prior to die mount

VERTICAL CIRCUITS INC

Wafer level surface passivation of stackable integrated circuit chips

TESSERA INC

Low-stress TSV design using conductive particles