Inventor

LEE NAE-IN

KR100 patents

⚠️ This page may combine multiple inventors who share the name “LEE NAE-IN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE NAE-IN

SAMSUNG ELECTRONICS CO LTD

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same

Dielectric layer for semiconductor device and method of manufacturing the same

CMOS integrated circuit devices and substrates having unstrained silicon active layers

Methods of forming wiring structures

Local SONOS-type structure having two-piece gate and self-aligned ONO and method for manufacturing the same

Method of forming a CMOS type semiconductor device having dual gates

SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon

Fan out wafer level package type semiconductor package and package on package type semiconductor package including the same

Dielectric layer for semiconductor device and method of manufacturing the same

Dielectric layer for semiconductor device and method of manufacturing the same

Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same

Post thermal treatment methods of forming high dielectric layers in integrated circuit devices

Flash memory having local SONOS structure using notched gate and manufacturing method thereof

Semiconductor device having gate all around type transistor and method of forming the same

MOS transistor having a T-shaped gate electrode and method for fabricating the same

Semiconductor device having gate all around type transistor and method of forming the same

Method of manufacturing CMOS semiconductor device

Semiconductor devices including a capping layer

Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices

MOS transistor having a T-shaped gate electrode

Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein

Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same

Method for forming SOI substrate

Semiconductor transistor using L-shaped spacer and method of fabricating the same

Method of fabricating a trench isolation structure having sidewall oxide layers with different thicknesses

Semiconductor device having hetero grain stack gate

Method for fabricating semiconductor device having multiple threshold voltages

Semiconductor devices including a capping layer

Semiconductor devices including a capping layer

Semiconductor devices including a stressor in a recess and methods of forming the same

Method of manufacturing an SOI type semiconductor that can restrain floating body effect

Semiconductor device having embedded strain-inducing pattern and method of forming the same

Semiconductor device having embedded strain-inducing pattern and method of forming the same

Semiconductor device having embedded strain-inducing pattern and method of forming the same

Field effect transistor having germanium nanorod and method of manufacturing the same

Method of manufacturing a non-volatile semiconductor memory device

Semiconductor transistor using L-shaped spacer

CMOS semiconductor device and method of manufacturing the same

Method for efficiently removing by-products produced in dry-etching

Semiconductor device

Method for fabricating substrate structure and substrate structure fabricated by using the method

Methods of manufacturing semiconductor devices including conductive structures

Semiconductor devices including a stressor in a recess and methods of forming the same

Methods of producing semiconductor devices including multiple stress films in interface area

SHIN DONG-SUK

Semiconductor devices including a stressor in a recess and methods of forming the same

Methods of forming semiconductor devices including a stressor in a recess

Semiconductor devices including a stressor in a recess and methods of forming the same

RHA SANGHO

Semiconductor devices including a capping layer and methods of forming semiconductor devices including a capping layer

KOREA ADVANCED INST SCI & TECH

Semiconductor device using N2O plasma oxide and a method of fabricating the same