Inventor
CHOI SAMUEL S
US44 patents
⚠️ This page may combine multiple inventors who share the name “CHOI SAMUEL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS9502350B1Nov 22, 2016
Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer
IBM49 citations98
US10177031B2Jan 8, 2019
Subtractive etch interconnects
IBM22 citations94
US9601426B1Mar 21, 2017
Interconnect structure having subtractive etch feature and damascene feature
IBM26 citations94
US10256186B2Apr 9, 2019
Interconnect structure having subtractive etch feature and damascene feature
IBM9 citations84
US9852980B2Dec 26, 2017
Interconnect structure having substractive etch feature and damascene feature
IBM7 citations84
US9536830B2Jan 3, 2017
High performance refractory metal / copper interconnects to eliminate electromigration
IBM14 citations84
US9455186B2Sep 27, 2016
Selective local metal cap layer formation for improved electromigration behavior
IBM4 citations84
US9293412B2Mar 22, 2016
Graphene and metal interconnects with reduced contact resistance
IBM9 citations84
US9202743B2Dec 1, 2015
Graphene and metal interconnects
IBM7 citations84
US9171801B2Oct 27, 2015
E-fuse with hybrid metallization
IBM19 citations84
US9142506B2Sep 22, 2015
E-fuse structures and methods of manufacture
IBM7 citations84
US9059170B2Jun 16, 2015
Electronic fuse having a damaged region
IBM12 citations84
US8916461B2Dec 23, 2014
Electronic fuse vias in interconnect structures
IBM8 citations84
US7045464B1May 16, 2006
Via reactive ion etching process
IBM13 citations82
US9893011B2Feb 13, 2018
Back-end electrically programmable fuse
IBM2 citations73
US9385038B2Jul 5, 2016
Selective local metal cap layer formation for improved electromigration behavior
IBM2 citations63
US9324655B2Apr 26, 2016
Modified via bottom for beol via efuse
IBM2 citations63
US9105641B2Aug 11, 2015
Profile control in interconnect structures
IBM2 citations63
US9076847B2Jul 7, 2015
Selective local metal cap layer formation for improved electromigration behavior
IBM1 citations63
US7442650B2Oct 28, 2008
Methods of manufacturing semiconductor structures using RIE process
IBM3 citations59
US9406560B2Aug 2, 2016
Selective local metal cap layer formation for improved electromigration behavior
IBM0 citations52
US9099468B2Aug 4, 2015
Electronic fuse vias in interconnect structures
IBM0 citations52
US8921167B2Dec 30, 2014
Modified via bottom for BEOL via efuse
IBM1 citations52
US9105638B2Aug 11, 2015
Via-fuse with low dielectric constant
IBM0 citations42
US9093452B2Jul 28, 2015
Electronic fuse with resistive heater
IBM0 citations42
GLOBALFOUNDRIES INC
9 patentsUS9755016B2Sep 5, 2017
Integration process to form microelectronic or micromechanical structures
GLOBALFOUNDRIES INC3 citations73
US9536842B2Jan 3, 2017
Structure with air gap crack stop
GLOBALFOUNDRIES INC4 citations73
US9425144B2Aug 23, 2016
Metal fuse structure for improved programming capability
GLOBALFOUNDRIES INC3 citations73
US9431346B2Aug 30, 2016
Graphene-metal E-fuse
GLOBALFOUNDRIES INC2 citations63
US10186482B2Jan 22, 2019
Self aligned via fuse
GLOBALFOUNDRIES INC0 citations52
US9337261B2May 10, 2016
Method of forming microelectronic or micromechanical structures
GLOBALFOUNDRIES INC0 citations52
US9257391B2Feb 9, 2016
Hybrid graphene-metal interconnect structures
GLOBALFOUNDRIES INC1 citations52
US9240376B2Jan 19, 2016
Self-aligned via fuse
GLOBALFOUNDRIES INC0 citations52
US10224236B2Mar 5, 2019
Forming air gap
GLOBALFOUNDRIES INC0 citations42
BONILLA GRISELDA
3 patentsUS8962467B2Feb 24, 2015
Metal fuse structure for improved programming capability
BONILLA GRISELDA6 citations84
US9034664B2May 19, 2015
Method to resolve hollow metal defects in interconnects
BONILLA GRISELDA3 citations63
US9059169B2Jun 16, 2015
E-fuse structures and methods of manufacture
BONILLA GRISELDA0 citations52