Inventor

LIEBMANN LARS

US93 patents

⚠️ This page may combine multiple inventors who share the name “LIEBMANN LARS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIEBMANN LARS

GLOBALFOUNDRIES INC

Integrated circuit structure incorporating stacked field effect transistors

Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method

Air-gap gate sidewall spacer and method

Method to form low resistance contact

Tall single-fin fin-type field effect transistor structures and methods

Middle of the line (MOL) contacts with two-dimensional self-alignment

Integrated circuit structure incorporating stacked field effect transistors and method

Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

Vertical field effect transistors incorporating U-shaped semiconductor bodies and methods

Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure

Methods of forming metallization lines on integrated circuit products and the resulting products

Self-aligned middle of the line (MOL) contacts

Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

Self-aligned cuts in an interconnect structure

Vertical field effect transistor with self-aligned contacts

Method of forming vertical FinFET device having self-aligned contacts

Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same

Air-gap gate sidewall spacer and method

Self-aligned middle of the line (MOL) contacts

Fin patterning for a fin-type field-effect transistor

Methods to control fin tip placement

Methods of forming an air gap adjacent a gate of a transistor and a gate contact above the active region of the transistor

Optimizing library cells with wiring in metallization layers

TOKYO ELECTRON LTD

Power distribution network for 3D logic and memory

Power wall integration for multiple stacked devices

3D complementary metal oxide semiconductor (CMOS) device and method of forming the same

Double cross-couple for two-row flip-flop using CFET

Power delivery network for CFET with buried power rails

CFET SRAM bit cell with two stacked device decks

Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices

CFET SRAM bit cell with three stacked device decks

Stacked three-dimensional field-effect transistors

Highly regular logic design for efficient 3D integration

3D directed self-assembly for nanostructures

Reverse contact and silicide process for three-dimensional logic devices

Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Architecture for monolithic 3D integration of semiconductor devices

Method for fabrication of high density logic and memory for advanced circuit architecture

Self-aligned method for vertical recess for 3D device integration

Method for automated standard cell design

Highly regular logic design for efficient 3D integration

Monolithic formation of a set of interconnects below active devices

High density logic formation using multi-dimensional laser annealing

Power delivery network for CFET with buried power rails

Method of manufacturing a semiconductor apparatus having stacked devices

GLOBALFOUNDRIES US INC

Metallization lines on integrated circuit products

Metallization lines on integrated circuit products

SIEMENS AG

Method of reducing loading variation during etch processing

IBM

Multilayer OPC for design aware manufacturing