Inventor

CHANEMOUGAME DANIEL

US105 patents

⚠️ This page may combine multiple inventors who share the name “CHANEMOUGAME DANIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANEMOUGAME DANIEL

GLOBALFOUNDRIES INC

Work function metal patterning for N-P space between active nanostructures

Hybrid gate-all-around (GAA) field effect transistor (FET) structure and method of forming

Integrated circuit structure incorporating stacked field effect transistors

Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method

Air-gap gate sidewall spacer and method

Method to form low resistance contact

Methods of forming gate contact structures and cross-coupled contact structures for transistor devices

Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillar

Integrated circuit structure incorporating stacked field effect transistors and method

Method of forming complementary nano-sheet/wire transistor devices with same depth contacts

Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor

Nanosheet field-effect transistors formed with sacrificial spacers

Gate-all-around field effect transistors with air-gap inner spacers and methods

Methods of forming gate contact structures and cross-coupled contact structures for transistor devices

Formation of bottom junction in vertical FET devices

Methods of forming metallization lines on integrated circuit products and the resulting products

Self-aligned middle of the line (MOL) contacts

Intergrated circuit structure including single diffusion break abutting end isolation region, and methods of forming same

Self-aligned cuts in an interconnect structure

Integrated circuit structure, gate all-around integrated circuit structure and methods of forming same

Air-gap gate sidewall spacer and method

Self-aligned middle of the line (MOL) contacts

Formation of bottom junction in vertical FET devices

Methods of forming bottom and top source/drain regions on a vertical transistor device

Cross-coupled contact structure on IC products and methods of making such contact structures

TOKYO ELECTRON LTD

Power wall integration for multiple stacked devices

3D complementary metal oxide semiconductor (CMOS) device and method of forming the same

Double cross-couple for two-row flip-flop using CFET

Power delivery network for CFET with buried power rails

CFET SRAM bit cell with two stacked device decks

Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices

CFET SRAM bit cell with three stacked device decks

Stacked three-dimensional field-effect transistors

Highly regular logic design for efficient 3D integration

3D directed self-assembly for nanostructures

Reverse contact and silicide process for three-dimensional logic devices

Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks

Method for fabrication of high density logic and memory for advanced circuit architecture

Self-aligned method for vertical recess for 3D device integration

Highly regular logic design for efficient 3D integration

Monolithic formation of a set of interconnects below active devices

IBM

Negative-capacitance steep-switch field effect transistor with integrated bi-stable resistive system

Steep-switch field effect transistor with integrated bi-stable resistive system

Steep-switch field effect transistor with integrated bi-stable resistive system

Steep-switch vertical field effect transistor

GLOBALFOUNDRIES US INC

Middle of the line self-aligned direct pattern contacts

Gate contact structures and cross-coupled contact structures for transistor devices

Metallization lines on integrated circuit products

Asymmetric gate cut isolation for SRAM

ST MICROELECTRONICS INC

Method for making semiconductor device with different fin sets