Inventor

SHEN XIAOWEI

CN49 patents

⚠️ This page may combine multiple inventors who share the name “SHEN XIAOWEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHEN XIAOWEI

IBM

Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint

Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements

Mechanism to save and restore cache and translation trace for fast context switch

Cost-conscious pre-emptive cache line displacement and relocation mechanisms

Architecture support of best-effort atomic transactions for multiprocessor systems

Enabling and disabling cache bypass using predicted cache line usage

Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies

Adaptive snoop-and-forward mechanisms for multiprocessor systems

Mechanisms and methods for using data access patterns

Scope-based cache coherence

Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing

Color-based cache monitoring

Methods and arrangements to manage on-chip memory to reduce memory latency

Adaptive mechanisms for supplying volatile data copies in multiprocessor systems

Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection

Cache line replacement monitoring and profiling

Cache residence prediction

Reservation required transactions

Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications

Adaptive snoop-and-forward mechanisms for multiprocessor systems

Latency-aware thread scheduling in non-uniform cache architecture systems

Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache

Cache line placement prediction for multiprocessor non-uniform cache architecture systems

Methods to maintain triangle ordering of coherence messages

Methods and arrangements to manage on-chip memory to reduce memory latency

Cache residence prediction

Location-aware cache-to-cache transfers

SHEN XIAOWEI

Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the buffer

System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory

Architecture support of memory access coloring

Architecture support of best-effort atomic transactions for multiprocessor systems

Memory access monitoring

Cache line replacement monitoring and profiling

Reservation required transactions

Cache coherence monitoring and feedback

Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems

MASSACHUSETTS INST TECHNOLOGY

Computer architecture for shared memory access

Computer architecture for shared memory access

Adaptive cache coherence protocols

Adaptive cache coherence protocols

DELL PRODUCTS LP

System and method to detect problematic code changes in firmware

Software-based log management

Automation test accelerator

Component to determine test steps conflicts in a firmware test

CAIN III HAROLD WADE

Method and system for a sharing buffer

CISCO TECH INC

Virtual cable modem termination system redundancy

BACON DAVID F

Systems and methods for indirect register access using status-checking and status-setting instructions

GANESH BRINDA

Reordering data responses using ordered indicia in a linked list

HZO INC

Use of combined masking techniques and/or combined material removal techniques to protectively coat electronic devices