Inventor
SUBBARAO SANJAY
US60 patents
⚠️ This page may combine multiple inventors who share the name “SUBBARAO SANJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICRON TECHNOLOGY INC
30 patentsUS11113198B2Sep 7, 2021
Timed data transfer between a host system and a memory sub-system
MICRON TECHNOLOGY INC5 citations84
US11734189B2Aug 22, 2023
Caching of logical-to-physical mapping information in a memory sub-system
MICRON TECHNOLOGY INC4 citations75
US11755495B2Sep 12, 2023
Storing a logical-to-physical mapping in NAND memory
MICRON TECHNOLOGY INC2 citations73
US11487666B2Nov 1, 2022
Timed data transfer between a host system and a memory sub-system
MICRON TECHNOLOGY INC1 citations73
US11409461B1Aug 9, 2022
Extending size of memory unit
MICRON TECHNOLOGY INC2 citations73
US11249896B2Feb 15, 2022
Logical-to-physical mapping of data groups with data locality
MICRON TECHNOLOGY INC5 citations73
US11164652B2Nov 2, 2021
Two-layer code with low parity cost for memory sub-systems
MICRON TECHNOLOGY INC3 citations73
US12079517B2Sep 3, 2024
Buffer allocation for reducing block transit penalty
MICRON TECHNOLOGY INC2 citations72
US12001721B2Jun 4, 2024
Multiple-pass programming of memory cells using temporary parity generation
MICRON TECHNOLOGY INC2 citations72
US11782643B2Oct 10, 2023
Partial execution of a write command from a host system
MICRON TECHNOLOGY INC0 citations63
US11782841B2Oct 10, 2023
Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
MICRON TECHNOLOGY INC0 citations63
US11709632B2Jul 25, 2023
Input/output size control between a host system and a memory sub-system
MICRON TECHNOLOGY INC0 citations63
US11676679B2Jun 13, 2023
Two-layer code with low parity cost for memory sub-systems
MICRON TECHNOLOGY INC1 citations63
US11294820B2Apr 5, 2022
Management of programming mode transitions to accommodate a constant size of data transfer between a host system and a memory sub-system
MICRON TECHNOLOGY INC1 citations63
US11204721B2Dec 21, 2021
Input/output size control between a host system and a memory sub-system
MICRON TECHNOLOGY INC1 citations63
US11113007B2Sep 7, 2021
Partial execution of a write command from a host system
MICRON TECHNOLOGY INC1 citations63
US12498886B2Dec 16, 2025
Buffer allocation for reducing block transit penalty
MICRON TECHNOLOGY INC0 citations62
US12481463B2Nov 25, 2025
Multiple-pass programming of memory cells using temporary parity generation
MICRON TECHNOLOGY INC0 citations62
US12216541B2Feb 4, 2025
Block failure protection for zone memory system
MICRON TECHNOLOGY INC0 citations62
US12130748B2Oct 29, 2024
Caching of logical-to-physical mapping information in a memory sub-system
MICRON TECHNOLOGY INC0 citations62
US12124380B2Oct 22, 2024
Storing a logical-to-physical mapping in NAND memory
MICRON TECHNOLOGY INC0 citations62
US12051479B2Jul 30, 2024
Memory block programming using defectivity information
MICRON TECHNOLOGY INC0 citations62
US12050809B2Jul 30, 2024
Multi-pass data programming in a memory sub-system having multiple dies and planes
MICRON TECHNOLOGY INC0 citations62
US12045168B2Jul 23, 2024
Timed data transfer between a host system and a memory sub-system
MICRON TECHNOLOGY INC0 citations62
US11914471B1Feb 27, 2024
Block failure protection for zone memory system
MICRON TECHNOLOGY INC1 citations62
US11726703B2Aug 15, 2023
Extending size of memory unit
MICRON TECHNOLOGY INC0 citations62
US11640354B2May 2, 2023
Logical-to-physical mapping of data groups with data locality
MICRON TECHNOLOGY INC0 citations62
US11573742B2Feb 7, 2023
Dynamic data placement for collision avoidance among concurrent write streams
MICRON TECHNOLOGY INC0 citations62
US11269552B2Mar 8, 2022
Multi-pass data programming in a memory sub-system having multiple dies and planes
MICRON TECHNOLOGY INC1 citations62
US11113006B2Sep 7, 2021
Dynamic data placement for collision avoidance among concurrent write streams
MICRON TECHNOLOGY INC1 citations62
WESTERN DIGITAL TECH INC
14 patentsUS10409511B1Sep 10, 2019
Multi-device storage system with distributed read/write processing
WESTERN DIGITAL TECH INC53 citations94
US10860508B2Dec 8, 2020
Offloaded disaggregated storage architecture
WESTERN DIGITAL TECH INC18 citations85
US10956071B2Mar 23, 2021
Container key value store for data storage devices
WESTERN DIGITAL TECH INC8 citations84
US10761929B2Sep 1, 2020
Data storage drive rebuild with parity generation offload using peer-to-peer data transfers
WESTERN DIGITAL TECH INC8 citations84
US10379948B2Aug 13, 2019
Redundancy coding stripe based on internal addresses of storage devices
WESTERN DIGITAL TECH INC11 citations84
US11281601B2Mar 22, 2022
Multi-device storage system with hosted services on peer storage devices
WESTERN DIGITAL TECH INC5 citations73
US11243837B2Feb 8, 2022
Data storage drive rebuild with parity generation offload using peer-to-peer data transfers
WESTERN DIGITAL TECH INC3 citations73
US10831603B2Nov 10, 2020
Rebuild assist using failed storage device
WESTERN DIGITAL TECH INC5 citations73
US10725941B2Jul 28, 2020
Multi-device storage system with hosted services on peer storage devices
WESTERN DIGITAL TECH INC4 citations73
US10725859B2Jul 28, 2020
Parity generation offload using peer-to-peer data transfers in data storage system
WESTERN DIGITAL TECH INC3 citations73
US10474528B2Nov 12, 2019
Redundancy coding stripe based on coordinated internal address scheme across multiple devices
WESTERN DIGITAL TECH INC5 citations73
US11054991B2Jul 6, 2021
Data storage system scale-out with local address remapping
WESTERN DIGITAL TECH INC1 citations62
US10769062B2Sep 8, 2020
Fine granularity translation layer for data storage devices
WESTERN DIGITAL TECH INC1 citations62
US10642525B2May 5, 2020
Multiple-stage data lifetime management for storage devices
WESTERN DIGITAL TECH INC1 citations62
HGST Netherlands BV
2 patentsADAPTEC INC
2 patentsARISTOS LOGIC CORP
1 patentARISTOS LOGIC COPORATION
1 patentShowing the top 50 of 60 patents by PatentIndex Score.