Inventor
SHAO KAI
CN19 patents
⚠️ This page may combine multiple inventors who share the name “SHAO KAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
13 patentsUS6133079AOct 17, 2000
Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions
CHARTERED SEMICONDUCTOR MFG88 citations98
US6297132B1Oct 2, 2001
Process to control the lateral doping profile of an implanted channel region
CHARTERED SEMICONDUCTOR MFG128 citations97
US6124194ASep 26, 2000
Method of fabrication of anti-fuse integrated with dual damascene process
CHARTERED SEMICONDUCTOR MFG90 citations97
US6117747ASep 12, 2000
Integration of MOM capacitor into dual damascene process
CHARTERED SEMICONDUCTOR MFG73 citations95
US6410394B1Jun 25, 2002
Method for forming self-aligned channel implants using a gate poly reverse mask
CHARTERED SEMICONDUCTOR MFG21 citations92
US6300201B1Oct 9, 2001
Method to form a high K dielectric gate insulator layer, a metal gate structure, and self-aligned channel regions, post source/drain formation
CHARTERED SEMICONDUCTOR MFG70 citations92
US6291307B1Sep 18, 2001
Method and structure to make planar analog capacitor on the top of a STI structure
CHARTERED SEMICONDUCTOR MFG36 citations92
US6156602ADec 5, 2000
Self-aligned precise high sheet RHO register for mixed-signal application
CHARTERED SEMICONDUCTOR MFG43 citations92
US6284594B1Sep 4, 2001
Formation of an interpoly capacitor structure using a chemical mechanical polishing procedure
CHARTERED SEMICONDUCTOR MFG16 citations83
US6489191B2Dec 3, 2002
Method for forming self-aligned channel implants using a gate poly reverse mask
CHARTERED SEMICONDUCTOR MFG8 citations73
US6159759ADec 12, 2000
Method to form liquid crystal displays using a triple damascene technique
CHARTERED SEMICONDUCTOR MFG7 citations73
US6861317B1Mar 1, 2005
Method of making direct contact on gate by using dielectric stop layer
CHARTERED SEMICONDUCTOR MFG10 citations72
US7382027B2Jun 3, 2008
MOSFET device with low gate contact resistance
CHARTERED SEMICONDUCTOR MFG4 citations61
UNIV CHONGQING POSTS & TELECOM
3 patentsUS10826742B2Nov 3, 2020
Method and system for multi-carrier time division multiplexing modulation/demodulation
UNIV CHONGQING POSTS & TELECOM1 citations70
US10541846B2Jan 21, 2020
Method and system for multi-carrier time division multiplexing modulation/demodulation
UNIV CHONGQING POSTS & TELECOM1 citations70
US11424974B2Aug 23, 2022
Method and system for multi-carrier time division multiplexing modulation/demodulation
UNIV CHONGQING POSTS & TELECOM0 citations59