Inventor

YADA SHINSUKE

JP35 patents

⚠️ This page may combine multiple inventors who share the name “YADA SHINSUKE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YADA SHINSUKE

SANDISK TECHNOLOGIES LLC

Three-dimensional memory device with self-aligned multi-level drain select gate electrodes

Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

Three-dimensional memory device with self-aligned drain select level isolation structures and method of making thereof

Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same

Three-dimensional memory device with separated source-side lines and method of making the same

Three-dimensional memory device with depletion region position control and method of erasing same using gate induced leakage

Three-dimensional memory device containing multilevel drain select gate isolation and methods of making the same

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Three-dimensional memory devices containing structures for controlling gate-induced drain leakage current and method of making the same

Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same

Multilevel interconnect structure and methods of manufacturing the same

Three-dimensional memory device with straddling drain select electrode lines and method of making thereof

Three-dimensional memory device containing self-aligned bit line contacts and methods for forming the same

Three-dimensional memory device with separated source-side lines and method of making the same

Three-dimensional memory device and method of erasing thereof from a source side

Three-dimensional memory device including bottle-shaped memory stack structures and drain-select gate electrodes having cylindrical portions

Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof

Three-dimensional memory device containing insulated gate located over a top source layer for applying GIDL erase voltage and method for manufacturing the same

On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same

Three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines

Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same

Three-dimensional memory device containing a pillar contact between channel and source and methods of making the same

Lateral transistors for selecting blocks in a three-dimensional memory array and methods for forming the same

SANDISK TECHNOLOGIES INC

Three dimensional NAND device with channel located on three sides of lower select gate and method of making thereof

Multilevel interconnect structure and methods of manufacturing the same

Three-dimensional memory devices containing memory stack structures with position-independent threshold voltage

Method of making a monolithic three dimensional NAND string using a select gate etch stop layer

Uniform thickness blocking dielectric portions in a three-dimensional memory structure

Batch contacts for multiple electrically conductive layers

Methods of fabricating memory device with spaced-apart semiconductor charge storage regions

Select gate bias gradation structure in NAND memory

Sub-block separation in NAND memory through word line based selectors

WESTERN DIGITAL TECH INC

Three-dimensional memory device with laterally separated source select electrodes and methods of forming the same

Three-dimensional memory device having controlled lateral isolation trench depth and methods of forming the same