Inventor
SUBRAMANIAN SRIDHAR
US27 patents
⚠️ This page may combine multiple inventors who share the name “SUBRAMANIAN SRIDHAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CISCO TECH INC
11 patentsUS9369473B2Jun 14, 2016
Method and system for extending network resources campus-wide based on user role and location
CISCO TECH INC5 citations73
US10003569B2Jun 19, 2018
Network resource sharing for routing and forwarding information
CISCO TECH INC2 citations72
US9641462B2May 2, 2017
Accelerating network convergence for layer 3 roams in a next generation network closet campus
CISCO TECH INC3 citations72
US11665095B2May 30, 2023
Fine-grained SD-WAN optimization services for cloud-native applications
CISCO TECH INC2 citations64
US11528270B2Dec 13, 2022
Network authorization in web-based or single sign-on authentication environments
CISCO TECH INC0 citations62
US9049127B2Jun 2, 2015
Methods and devices for providing service clustering in a trill network
CISCO TECH INC2 citations61
US10673850B2Jun 2, 2020
Network authorization in web-based or single sign-on authentication environments
CISCO TECH INC0 citations52
US9648005B2May 9, 2017
Method and system for extending network resources campus-wide based on user role and location
CISCO TECH INC0 citations52
US9590906B2Mar 7, 2017
Network resource sharing for routing and forwarding information
CISCO TECH INC0 citations51
US9680751B2Jun 13, 2017
Methods and devices for providing service insertion in a TRILL network
CISCO TECH INC0 citations50
US10462007B2Oct 29, 2019
Network address transparency through user role authentication
CISCO TECH INC0 citations38
XILINX INC
5 patentsUS11288222B1Mar 29, 2022
Multi-die integrated circuit with data processing engine array
XILINX INC8 citations86
US12001367B2Jun 4, 2024
Multi-die integrated circuit with data processing engine array
XILINX INC2 citations73
US11693808B2Jul 4, 2023
Multi-die integrated circuit with data processing engine array
XILINX INC3 citations73
US11386020B1Jul 12, 2022
Programmable device having a data processing engine (DPE) array
XILINX INC2 citations69
US7746116B1Jun 29, 2010
Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysis
XILINX INC5 citations58
MANOVIT CHAIYASIT
3 patentsUS8099703B1Jan 17, 2012
Method and system for verifying power-optimized electronic designs using equivalency checking
MANOVIT CHAIYASIT14 citations82
US8219946B1Jul 10, 2012
Method for clock gating circuits
MANOVIT CHAIYASIT11 citations80
US8423935B1Apr 16, 2013
Method and apparatus for verifying output-based clock gating
MANOVIT CHAIYASIT4 citations58
ADVANCED MICRO DEVICES INC
2 patentsUS6624681B1Sep 23, 2003
Circuit and method for stopping a clock tree while maintaining PLL lock
ADVANCED MICRO DEVICES INC21 citations89
US6449759B1Sep 10, 2002
System and method for automatic insertion and placement of repeater buffers on an integrated circuit floor plan
ADVANCED MICRO DEVICES INC10 citations72
NARAYANAN SRIDHAR
2 patentsKEYSSA INC
2 patentsUS9940295B2Apr 10, 2018
Extremely high frequency systems and methods of operating the same to establish USB data transport protocols
KEYSSA INC2 citations71
US10592461B2Mar 17, 2020
Extremely high frequency systems and methods of operating the same to establish USB data transport protocols
KEYSSA INC0 citations51