Inventor

LABERGE PAUL A

US114 patents

⚠️ This page may combine multiple inventors who share the name “LABERGE PAUL A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LABERGE PAUL A

MICRON TECHNOLOGY INC

Memory system and method using stacked memory device dice, and system using the memory system

Multi-serial interface stacked-die memory architecture

On-die termination snooping for 2T applications in a memory system implementing non-self-terminating ODT schemes

Dynamic command and/or address mirroring system and method for memory modules

Delay line synchronizer apparatus and method

Method and apparatus for data transfer

Memory system and method using stacked memory device dice, and system using the memory system

Memory devices with buffered command address bus

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing

Bus arbitration

Device for blocking bus transactions during reset

Memory system and method using stacked memory device dice, and system using the memory system

System and method for controlling timing of output signals

Capturing read data

Method and apparatus for data transfer

System and method for an asynchronous data buffer having buffer write and read pointers

System and method for controlling timing of output signals

Modified persistent auto precharge command protocol system and method for memory devices

Method and apparatus for data transfer

Bus arbitration using monitored windows of time

Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing

Cas latency select utilizing multilevel signaling

Method and apparatus for an adjustable delay circuit having arranged serially coarse stages received by a fine delay stage

Capturing read data

System and method for regulating data capture in response to data strobe using preamble, postamble and strobe signature

Adjusting and measuring the timing of a data strobe signal with a first delay line and through additional delay line adapted to receive pulse signal

Memory cache with sequential page indicators

Method and apparatus to reduce memory read latency

Reducing memory latency by not performing bank conflict checks on idle banks

Circuit synthesis time budgeting based upon wireload information

Method for modifying an integrated circuit

Stacked device remapping and repair

Method and system for apportioning computer bus bandwidth

Latency reduction using negative clock edge and read flags

Latency reduction using negative clock edge and read flags

MICRON ELECTRONICS INC

Method of peer-to-peer mastering over a computer bus

Programmable logic block in an integrated circuit

Method and system for concurrent computer transaction processing

System for peer-to-peer mastering over a computer bus

Method and system for apportioning computer bus bandwith

Method and system for concurrent computer transaction processing

Method and system for apportioning computer bus bandwidth

Method and system for apportioning computer bus bandwidth

UNISYS CORP

Programmable error detect/mask utilizing bus history stack

Multiple power domain power loss detection and interface disable

JOHNSON JAMES BRIAN

Strobe apparatus, systems, and methods

JEDDELOH JOE M

Switched interface stacked-die memory architecture

ROUND ROCK RES LLC

Memory devices with buffered command address bus

LABERGE PAUL A

System and method for controlling timing of output signals

MIRCRON TECHNOLOGY INC

Write clock and data window tuning based on rank select