P

Inventor

JOHNSON ROBERT B

US43 patents
⚠️ This page may combine multiple inventors who share the name “JOHNSON ROBERT B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HONEYWELL INF SYSTEMS

25 patents
US4507730AMar 26, 1985

Memory system with automatic memory configuration

HONEYWELL INF SYSTEMS80 citations96
US4468731AAug 28, 1984

Identification apparatus for use in a controller to facilitate the diagnosis of faults

HONEYWELL INF SYSTEMS101 citations96
US4369510AJan 18, 1983

Soft error rewrite control system

HONEYWELL INF SYSTEMS73 citations96
US4366538ADec 28, 1982

Memory controller with queue control apparatus

HONEYWELL INF SYSTEMS83 citations96
US4359771ANov 16, 1982

Method and apparatus for testing and verifying the operation of error control apparatus within a memory

HONEYWELL INF SYSTEMS62 citations96
US4545010AOct 1, 1985

Memory identification apparatus and method

HONEYWELL INF SYSTEMS63 citations95
US4558429ADec 10, 1985

Pause apparatus for a memory controller with interleaved queuing apparatus

HONEYWELL INF SYSTEMS39 citations93
US4388684AJun 14, 1983

Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources

HONEYWELL INF SYSTEMS30 citations93
US4370712AJan 25, 1983

Memory controller with address independent burst mode capability

HONEYWELL INF SYSTEMS38 citations93
US4366539ADec 28, 1982

Memory controller with burst mode capability

HONEYWELL INF SYSTEMS45 citations93
US4323965AApr 6, 1982

Sequential chip select decode apparatus and method

HONEYWELL INF SYSTEMS88 citations93
US4044330AAug 23, 1977

Power strobing to achieve a tri state

HONEYWELL INF SYSTEMS34 citations93
US4432055AFeb 14, 1984

Sequential word aligned addressing apparatus

HONEYWELL INF SYSTEMS28 citations92
US4185323AJan 22, 1980

Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations

HONEYWELL INF SYSTEMS32 citations92
US4060794ANov 29, 1977

Apparatus and method for generating timing signals for latched type memories

HONEYWELL INF SYSTEMS38 citations91
US4451880AMay 29, 1984

Memory controller with interleaved queuing apparatus

HONEYWELL INF SYSTEMS24 citations82
US4361869ANov 30, 1982

Multimode memory system using a multiword common bus for double word and single word transfer

HONEYWELL INF SYSTEMS27 citations82
US4236203ANov 25, 1980

System providing multiple fetch bus cycle operation

HONEYWELL INF SYSTEMS22 citations82
US4190901AFeb 26, 1980

Printed circuit board apparatus which facilitates fabrication of units comprising a data processing system

HONEYWELL INF SYSTEMS7 citations73
US4030084AJun 14, 1977

Substrate bias voltage generated from refresh oscillator

HONEYWELL INF SYSTEMS11 citations73
US4376972AMar 15, 1983

Sequential word aligned address apparatus

HONEYWELL INF SYSTEMS15 citations72
US4319324AMar 9, 1982

Double word fetch system

HONEYWELL INF SYSTEMS14 citations72
US4255852AMar 17, 1981

Method of constructing a number of different memory systems

HONEYWELL INF SYSTEMS5 citations63
US3967139AJun 29, 1976

Apparatus for enhancing output characteristics of voltage driver circuits

HONEYWELL INF SYSTEMS3 citations60
US4302735ANov 24, 1981

Delay line compensation network

HONEYWELL INF SYSTEMS1 citations52

KIMBERLY CLARK CO

4 patents

K & R EQUIPMENT INC

2 patents

EASTMAN KODAK CO

2 patents

BANYAN WATER INC

2 patents

ENDEVCO CORP

1 patent

HELMUT E W MASCH

1 patent

BOGA RAMESHBABU

1 patent

MASCH HELMUT E W

1 patent

RAYTHEON CO

1 patent

NAT SEMICONDUCTOR CORP

1 patent

WILLAMETTE IND INC

1 patent

JOHNSON ROBERT B

1 patent