Inventor

NIBBY JR CHESTER M

US36 patents

⚠️ This page may combine multiple inventors who share the name “NIBBY JR CHESTER M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NIBBY JR CHESTER M

HONEYWELL INF SYSTEMS

Memory system with automatic memory configuration

Identification apparatus for use in a controller to facilitate the diagnosis of faults

Soft error rewrite control system

Memory controller with queue control apparatus

Method and apparatus for testing and verifying the operation of error control apparatus within a memory

Memory identification apparatus and method

Data processing system having centralized memory refresh

Memory present apparatus

Pause apparatus for a memory controller with interleaved queuing apparatus

Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources

Memory controller with address independent burst mode capability

Memory controller with burst mode capability

Sequential chip select decode apparatus and method

Apparatus and method for storing parity encoded data from a plurality of input/output sources

Power strobing to achieve a tri state

Remap method and apparatus for a memory system which uses partially good memory devices

Sequential word aligned addressing apparatus

Apparatus and method for generating timing signals for latched type memories

Partial defective chip memory support system

Memory controller with interleaved queuing apparatus

Multimode memory system using a multiword common bus for double word and single word transfer

Error detection and correction locator circuits

Rotating chip selection technique and apparatus

Sequential word aligned address apparatus

Double word fetch system

Method of constructing a number of different memory systems

Delay line compensation network

BULL HN INFORMATION SYST

Cache resiliency in processing a variety of address faults

High speed burst read address generation with high speed transfer

High performance burst read data transfer operation

Apparatus for loading and verifying a control store memory of a central subsystem

Processor bus access

Data processing system having a bus command generated by one subsystem on behalf of another subsystem

Power-on sequencing apparatus for initializing and testing a system processing unit

Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function

HONEYWELL BULL

Address transform method and apparatus for transferring addresses