Inventor
FAUCHER MARC R
US19 patents
⚠️ This page may combine multiple inventors who share the name “FAUCHER MARC R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS5963464AOct 5, 1999
Stackable memory card
IBM203 citations98
US5459842AOct 17, 1995
System for combining data from multiple CPU write requests via buffers and using read-modify-write operation to write the combined data to the memory
IBM182 citations97
US6185718B1Feb 6, 2001
Memory card design with parity and ECC for non-parity and non-ECC systems
IBM106 citations96
US6052818AApr 18, 2000
Method and apparatus for ECC bus protection in a computer system with non-parity memory
IBM66 citations96
US5404543AApr 4, 1995
Method and system for reducing an amount of power utilized by selecting a lowest power mode from a plurality of power modes
IBM104 citations96
US6532520B1Mar 11, 2003
Method and apparatus for allocating data and instructions within a shared cache
IBM62 citations95
US6108730AAug 22, 2000
Memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket
IBM54 citations95
US6457155B1Sep 24, 2002
Method for making a memory card adapter insertable into a motherboard memory card socket comprising a memory card receiving socket having the same configuration as the motherboard memory card socket
IBM25 citations92
US5959845ASep 28, 1999
Universal chip carrier connector
IBM43 citations92
US5548746AAug 20, 1996
Non-contiguous mapping of I/O addresses to use page protection of a process
IBM27 citations91
US5448521ASep 5, 1995
Connecting a short word length non-volatile memory to a long word length address/data multiplexed bus
IBM20 citations90
US6578155B1Jun 10, 2003
Data processing system with adjustable clocks for partitioned synchronous interfaces
IBM13 citations84
US7962695B2Jun 14, 2011
Method and system for integrating SRAM and DRAM architecture in set associative cache
IBM14 citations83
US5969997AOct 19, 1999
Narrow data width DRAM with low latency page-hit operations
IBM8 citations73
US6178467B1Jan 23, 2001
Microprocessor system requests burstable access to noncacheable memory areas and transfers noncacheable address on a bus at burst mode
IBM13 citations72
US7882302B2Feb 1, 2011
Method and system for implementing prioritized refresh of DRAM based cache
IBM5 citations62
US8019970B2Sep 13, 2011
Three-dimensional networking design structure
IBM0 citations52
US7865694B2Jan 4, 2011
Three-dimensional networking structure
IBM0 citations52