Inventor

KUDELKA STEPHAN

US45 patents

⚠️ This page may combine multiple inventors who share the name “KUDELKA STEPHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUDELKA STEPHAN

INFINEON TECHNOLOGIES AG

Method of preparing buried LOCOS collar in trench DRAMS

Etch selectivity inversion for etching along crystallographic directions in silicon

Buried strap formation without TTO deposition

Semiconductor structures and manufacturing methods

Process flow for sacrificial collar with poly mask

Structure and method for improved isolation in trench storage cells

Method of forming a vertically oriented device in an integrated circuit

Integrated circuit vertical trench device and method of forming thereof

Dual gate oxide process for uniform oxide thickness

Semiconductor trench structure

Process flow for two-step collar in DRAM preparation

Integrated circuit trench device with a dielectric collar stack, and method of forming thereof

Method for patterning ceramic layers

Etch process for recessing polysilicon in trench structures

Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices

Trench capacitor with buried strap

High aspect ratio PBL SiN barrier formation

Semiconductor structures and manufacturing methods

Low temperature self-aligned collar formation

Method for fabricating a trench capacitor with an insulation collar

Spacer formation process using oxide shield

Process to suppress lithography at a wafer edge

Method for fabricating trench capacitor with insulation collar electrically connected to substrate through buried contact, in particular, for a semiconductor memory cell

Method for expanding a trench in a semiconductor structure

Manufacturing method for a trench capacitor having an isolation collar electrically connected with a substrate on a single side via a buried contact for use in a semiconductor memory cell

Low temperature sacrificial oxide formation

Trench capacitor with buried strap

Method for fabricating a capacitor

Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact

IBM

Method for hybrid DRAM cell utilizing confined strap isolation

Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation

Process flow for capacitance enhancement in a DRAM trench

Process flow for thick isolation collar with reduced length

Method for surface roughness enhancement in semiconductor capacitor manufacturing

Selective etching to increase trench surface area

Method of making encapsulated spacers in vertical pass gate DRAM and damascene logic gates

INFINEON TECHNOLOGIES CORP

Single sided buried strap

Temperature controlled gassification of deionized water for megasonic cleaning of semiconductor wafers

Temperature controlled degassification of deionized water for megasonic cleaning of semiconductor wafers

Buried strap poly etch back (BSPE) process

Rough oxide hard mask for DT surface area enhancement for DT DRAM

QIMONDA AG

Deposition method for a transition-metal-containing dielectric

Method of producing a conductive layer including two metal nitrides

Stacked capacitor and method for producing stacked capacitors for dynamic memory cells

SIEMENS AG

Method of manufacturing semiconductor structures including a pair of MOSFETs