Inventor

TEWS HELMUT HORST

US41 patents

⚠️ This page may combine multiple inventors who share the name “TEWS HELMUT HORST”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TEWS HELMUT HORST

INFINEON TECHNOLOGIES AG

Moisture barrier capacitors in semiconductor components

Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor

Buried strap formation without TTO deposition

Semiconductor structures and manufacturing methods

Low resistivity deep trench fill for DRAM and EDRAM applications

Process flow for sacrificial collar with poly mask

Method of forming a vertically oriented device in an integrated circuit

Integrated circuit vertical trench device and method of forming thereof

Sacrificial collar method for improved deep trench processing

Reduction of orientation dependent oxidation for vertical sidewalls of semiconductor substrates

Dual gate oxide process for uniform oxide thickness

Orientation independent oxidation of silicon

Process flow for two-step collar in DRAM preparation

Process flow for sacrificial collar scheme with vertical nitride mask

Integrated circuit trench device with a dielectric collar stack, and method of forming thereof

Process of fabricating DRAM cells with collar isolation layers

High aspect ratio PBL SiN barrier formation

Process for improving the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication

Plasma doping for DRAM with deep trenches and hemispherical grains

Control of oxide thickness in vertical transistor structures

Moisture barrier capacitors in semiconductor components

Semiconductor structures and manufacturing methods

Strained semiconductor device and method of making the same

Process flow for sacrificial collar with polysilicon void

Methods for producing a tunnel field-effect transistor

Strained semiconductor device and method of making the same

Strained semiconductor device and method of making the same

IBM

Process flow for capacitance enhancement in a DRAM trench

Method of forming self-limiting polysilicon LOCOS for DRAM cell

Vertical hard mask

Method for surface roughness enhancement in semiconductor capacitor manufacturing

Selective etching to increase trench surface area

INFINEON TECHNOLOGIES CORP

Method of forming a hemispherical grained capacitor

Process for improving the thickness uniformity of a thin layer in semiconductor wafer fabrication

Rough oxide hard mask for DT surface area enhancement for DT DRAM

BARTH HANS-JOACHIM

Semiconductor devices and methods of manufacture thereof

Methods of forming moisture barrier capacitors in semiconductor components

Capacitor having a plurality of parallel conductive members

SIEMENS AKTIENGESELLSCHARFT

Combined preanneal/oxidation step using rapid thermal processing

QIMONDA AG

Method of implanting using a shadow effect

TEWS HELMUT HORST

Strained semiconductor device and method of making the same