Inventor
AJMERA ATUL C
US15 patents
⚠️ This page may combine multiple inventors who share the name “AJMERA ATUL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
13 patentsUS7759206B2Jul 20, 2010
Methods of forming semiconductor devices using embedded L-shape spacers
IBM118 citations98
US6991979B2Jan 31, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM52 citations96
US6566210B2May 20, 2003
Method of improving gate activation by employing atomic oxygen enhanced oxidation
IBM35 citations92
US6566198B2May 20, 2003
CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufacture
IBM32 citations92
US6506649B2Jan 14, 2003
Method for forming notch gate having self-aligned raised source/drain structure
IBM33 citations92
US6440807B1Aug 27, 2002
Surface engineering to prevent EPI growth on gate poly during selective EPI processing
IBM31 citations92
US6057220AMay 2, 2000
Titanium polycide stabilization with a porous barrier
IBM36 citations92
US6013583AJan 11, 2000
Low temperature BPSG deposition process
IBM50 citations92
US6437377B1Aug 20, 2002
Low dielectric constant sidewall spacer using notch gate process
IBM21 citations89
US6602759B2Aug 5, 2003
Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon
IBM7 citations74
US7091128B2Aug 15, 2006
Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
IBM6 citations73
US6900092B2May 31, 2005
Surface engineering to prevent epi growth on gate poly during selective epi processing
IBM11 citations73
US6642156B2Nov 4, 2003
Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectrics
IBM11 citations73