Inventor
KUHN MARKUS
US32 patents
⚠️ This page may combine multiple inventors who share the name “KUHN MARKUS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
18 patentsUS6890807B2May 10, 2005
Method for making a semiconductor device having a metal gate electrode
INTEL CORP67 citations98
US7074680B2Jul 11, 2006
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP64 citations97
US6689675B1Feb 10, 2004
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP91 citations97
US7727892B2Jun 1, 2010
Method and apparatus for forming metal-metal oxide etch stop/barrier for integrated circuit interconnects
INTEL CORP16 citations92
US7084038B2Aug 1, 2006
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP13 citations92
US6787440B2Sep 7, 2004
Method for making a semiconductor device having an ultra-thin high-k gate dielectric
INTEL CORP41 citations92
US7339271B2Mar 4, 2008
Metal-metal oxide etch stop/barrier for integrated circuit interconnects
INTEL CORP9 citations83
US9711598B2Jul 18, 2017
Two-dimensional condensation for uniaxially strained semiconductor fins
INTEL CORP3 citations73
US6794755B2Sep 21, 2004
Surface alteration of metal interconnect in integrated circuits for electromigration and adhesion improvement
INTEL CORP11 citations72
US7122870B2Oct 17, 2006
Methods of forming a multilayer stack alloy for work function engineering
INTEL CORP7 citations70
US6849509B2Feb 1, 2005
Methods of forming a multilayer stack alloy for work function engineering
INTEL CORP10 citations70
US7420254B2Sep 2, 2008
Semiconductor device having a metal gate electrode
INTEL CORP4 citations63
US10897009B2Jan 19, 2021
Resistive memory cells and precursors thereof, methods of making the same, and devices including the same
INTEL CORP0 citations62
US7709909B2May 4, 2010
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP1 citations62
US7442983B2Oct 28, 2008
Method for making a semiconductor device having a high-k gate dielectric
INTEL CORP2 citations62
US7192890B2Mar 20, 2007
Depositing an oxide
INTEL CORP2 citations61
US10304929B2May 28, 2019
Two-dimensional condensation for uniaxially strained semiconductor fins
INTEL CORP0 citations52
US9680013B2Jun 13, 2017
Non-planar device having uniaxially strained semiconductor body and method of making same
INTEL CORP0 citations52
KAVALIEROS JACK T
3 patentsUS8211772B2Jul 3, 2012
Two-dimensional condensation for uniaxially strained semiconductor fins
KAVALIEROS JACK T72 citations97
US9159835B2Oct 13, 2015
Two-dimensional condensation for uniaxially strained semiconductor fins
KAVALIEROS JACK T3 citations62
US9419140B2Aug 16, 2016
Two-dimensional condensation for uniaxially strained semiconductor fins
KAVALIEROS JACK T0 citations51
CEA STEPHEN M
3 patentsUS8558279B2Oct 15, 2013
Non-planar device having uniaxially strained semiconductor body and method of making same
CEA STEPHEN M15 citations92
US8269283B2Sep 18, 2012
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
CEA STEPHEN M18 citations92
US8487348B2Jul 16, 2013
Methods and apparatus to reduce layout based strain variations in non-planar transistor structures
CEA STEPHEN M8 citations83