Inventor

JEDDELOH JOSEPH

US46 patents

⚠️ This page may combine multiple inventors who share the name “JEDDELOH JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JEDDELOH JOSEPH

MICRON TECHNOLOGY INC

Pipelined memory controller

Method of processing memory requests in a pipelined memory controller

Memory hub and access method having internal prefetch buffers

Calibration of memory circuits

Pipelined memory controller

Method of bus arbitration using requesting device bandwidth and priority ranking

Method for memory error handling

Method of implementing an accelerated graphics port for a multiple memory controller computer system

Buffer control system and method for a memory system having outstanding read and write request buffers

Processing memory requests in a pipelined memory controller

Method of implementing an accelerated graphics/port for a multiple memory controller computer system

Embedded DRAM cache memory and method having reduced latency

Method of implementing an accelerated graphics port for a multiple memory controller computer system

System and method for caching data based on identity of requestor

Method and apparatus for efficient bus arbitration

Method of processing memory transactions in a computer system having dual system memories and memory controllers

Embedded DRAM cache memory and method having reduced latency

Accelerated graphics port for a multiple memory controller computer system

System and method for controlling multi-bank embedded DRAM

System and method for caching data based on identity of requestor

Accelerated graphics port for a multiple memory controller computer system

System and method of processing memory requests in a pipelined memory controller

Calibration of memory circuits

Pipelined memory controller

Apparatus for flexibly allocating request/grant pins between multiple bus controllers

Method for flexibly allocating request/grant pins between multiple bus controllers

Apparatus and methods for a physical layout of simultaneously sub-accessible memory modules

MICRON ELECTRONICS INC

Pipelined memory controller

System and method for remapping defective memory locations

System and method for remapping defective memory locations

System for remapping defective memory bit sets

Accelerated graphics port for multiple memory controller computer system

Memory fault correction system and method

Apparatus for performing a low latency memory read with concurrent snoop

Method for remapping defective memory bit sets to non-defective memory bit sets

Method for accelerating memory bandwidth

Computer system with a switch interconnector for computer devices

System for method memory error handling

System for memory error handling

Segmented memory system employing different interleaving scheme for each different memory segment

System and method for accelerated remapping of defective memory locations

Low latency memory read with concurrent pipe lined snoops

System for accelerating memory bandwidth

LEE TERRY R

Memory hub and access method having internal prefetch buffers

ROUND ROCK RES LLC

Method of implementing an accelerated graphics port for a multiple memory controller computer system

JEDDELOH JOSEPH

Method of implementing an accelerated graphics port for a multiple memory controller computer system