Inventor

ROTONDARO ANTONIO L P

US49 patents

⚠️ This page may combine multiple inventors who share the name “ROTONDARO ANTONIO L P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROTONDARO ANTONIO L P

TEXAS INSTRUMENTS INC

Multiple work function gates

Annealing of high-k dielectric materials

Selective removal of TixNy

Gate structure and method

Gate dielectric and method

High temperature interface layer growth for high-k gate dielectric

Anneal sequence for high-κ film property optimization

High-k gate dielectric with uniform nitrogen profile and methods for making the same

Method for fabricating transistor gate structures and gate dielectrics thereof

Method of making multiple work function gates by implanting metals with metallic alloying additives

Gate dielectric and method

Gate structure and method

Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide

Ultra-thin SiO2using N2O as the oxidant

Dry etch process for small-geometry metal gates over thin gate dielectric

Method for fabricating split gate transistor device having high-k dielectrics

Plasma process for organic residue removal from copper

Method for integrating high-k dielectrics in transistor devices

Silicon processing method

Gate structure and method

Gate structure and method

Integrated circuits with composite gate dielectric

Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures

Gate structure and method

Dry process for post oxide etch residue removal

Gate dielectric and method

Method to selectively recess ETCH regions on a wafer surface using capoly as a mask

Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound

Method and system for forming dual work function gate electrodes in a semiconductor device

Gate structure and method

Method for controlling defects in gate dielectrics

Dual work function gate electrodes using doped polysilicon and a metal silicon germanium compound

Semiconductor device manufactured using a laminated stress layer

Gate dielectric and method

Encapsulated spacer with low dielectric constant material to reduce the parasitic capacitance between gate and drain in CMOS technology

Method and system for forming dual work function gate electrodes in a semiconductor device

Method to improve the uniformity and reduce the surface roughness of the silicon dielectric interface

Simplifying conductive plate/via isolation

Multi-step process for patterning a metal gate electrode

Complementary transistors having respective gates formed from a metal and a corresponding metal-silicide

TOKYO ELECTRON LTD

Colloidal silica growth inhibitor and associated method and system

Process and apparatus for processing a nitride structure without silica deposition

Process and apparatus for processing a nitride structure without silica deposition

Colloidal silica growth inhibitor and associated method and system

ROTONDARO ANTONIO L P

Body contacted transistor with reduced parasitic capacitance

Body contacted transistor with reduced parasitic capacitance

TEXAS INSTR INCROPORATED

Multi-step process for patterning a metal gate electrode

LI ZHENGWEN

Selectively self-assembling oxygen diffusion barrier

IMEC INTER UNI MICRO ELECTR

Metal rinsing process with controlled metal microcorrosion reduction