Inventor

MCGRATH KEVIN J

US40 patents

⚠️ This page may combine multiple inventors who share the name “MCGRATH KEVIN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MCGRATH KEVIN J

ADVANCED MICRO DEVICES INC

Method of controlling access to control registers of a microprocessor

Method for selectively disabling interrupts on a secure execution mode-capable processor

Processor including a translation unit for selectively translating virtual addresses of different sizes using a plurality of paging tables and mapping mechanisms

Providing global translations with address space numbers

Microcode patch device and method for patching microcode using match registers and patch routines

Executing system management mode code as virtual machine guest

Method and apparatus for controlling interrupts in a secure execution mode-capable processor

Method of controlling access to model specific registers of a microprocessor

Double prefix overrides to provide 16-bit operand size in a 32/64 operating mode

Alternate fault handler

Memory address checking in a proccesor that support both a segmented and a unsegmented address space

Controlling access to a control register of a microprocessor

Processor which overrides default operand size for implicit stack pointer references and near branches

Initialization of a computer system including a secure execution mode-capable processor

Computer system including a secure execution mode-capable CPU and a security services processor connected via a secure communication path

Method and apparatus for controlling operation of a secure execution mode-capable processor in system management mode

Processor which overrides default operand size for implicit stack pointer references and near branches

Mechanism for selectively blocking peripheral device accesses to system memory

Multiple entry points for system call instructions

Method of controlling access to an address translation data structure of a computer system

Establishing a mode indication responsive to two or more indications

Flags handling for system call instructions

Mode dependent segment use with mode independent segment update

Apparatus and method for generating 64 bit displacement and immediate values

Address size and operand size prefix overrides for default sizes defined by an operating mode of a processor

Apparatus and method for generating 64 bit addresses using a 32 bit adder

Selective zero extension based on operand size

Establishing an operating mode in a processor

Variable state save formats based on operand size of state save instruction

Processing node including a plurality of processor cores and an interconnect configurable in a test-mode to cause first and second transaction source indicators to be interchanged

Establishing an operating mode in a processor

Uniform register addressing using prefix byte

Instruction causing swap of base address from segment register with address from another register

Processor, method and apparatus with descriptor table storing segment descriptors of varying size

IP relative addressing

Call gate expansion for 64 bit addressing

Apparatus and method for generating virtual addresses for different memory models

Adaptive extension of leases for entries in a translation lookaside buffer

Using leases for entries in a translation lookaside buffer

KLAIBER ALEXANDER C

Virtualization of real mode execution