Inventor

TRIVEDI PRADEEP R

US29 patents

⚠️ This page may combine multiple inventors who share the name “TRIVEDI PRADEEP R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRIVEDI PRADEEP R

SUN MICROSYSTEMS INC

Compensation technique to mitigate aging effects in integrated circuit components

Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generators

Dual edge-triggered flip-flop design with asynchronous programmable reset

Deskewing global clock skew using localized DLLs

Programmable current source adjustment of leakage current for phase locked loop

Method for reducing supply noise near an on-die thermal sensor

Embedded integrated circuit aging sensor system

Clock skew reduction using active shields

Programmable current source adjustment of leakage current for delay locked loop

Measuring skew using on-chip sampling

Programmable leakage current offset for delay locked loop

Programmable leakage current offset for phase locked loop

Method for reducing peak to peak jitter in a dual-loop delay locked loop

System level reduction of clock skew based on local thermal profiling

Variation reduction technique for charge pump transistor aging

Reducing voltage variation in a phase locked loop

Verifying on-chip decoupling capacitance

Apparatus for reducing the supply noise near large clock drivers

Non-integer division of frequency

Reducing PECL voltage variation

Method and apparatus for receiver circuit tuning

DLL static phase error measurement technique

APPLE INC

Chip to chip interface with scalable bandwidth

Clock gater with test features and low setup time

Modular programmable delay line blocks for use in a delay locked loop

Chip to chip interface with scalable bandwidth

Low latency flop circuit

Delay locked loop including a mechanism for reducing lock time

CAMPBELL BRIAN J

Clock gater with test features and low setup time