Inventor
TRUONG THUONG QUANG
US32 patents
⚠️ This page may combine multiple inventors who share the name “TRUONG THUONG QUANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
27 patentsUS6820143B2Nov 16, 2004
On-chip data transfer in multi-processor system
IBM58 citations96
US6760819B2Jul 6, 2004
Symmetric multiprocessor coherence mechanism
IBM56 citations96
US7546393B2Jun 9, 2009
System for asynchronous DMA command completion notification wherein the DMA command comprising a tag belongs to a plurality of tag groups
IBM23 citations92
US7200688B2Apr 3, 2007
System and method asynchronous DMA command completion notification by accessing register via attached processing unit to determine progress of DMA command
IBM21 citations92
US7103748B2Sep 5, 2006
Memory management for real-time applications
IBM21 citations92
US7093080B2Aug 15, 2006
Method and apparatus for coherent memory structure of heterogeneous processor systems
IBM25 citations92
US6981072B2Dec 27, 2005
Memory management in multiprocessor system
IBM34 citations92
US7669013B2Feb 23, 2010
Directory for multi-node coherent bus
IBM9 citations84
US7055004B2May 30, 2006
Pseudo-LRU for a locking cache
IBM13 citations84
US7225277B2May 29, 2007
Proxy direct memory access
IBM12 citations81
US7114035B2Sep 26, 2006
Software-controlled cache set management with software-generated class identifiers
IBM8 citations74
US7114042B2Sep 26, 2006
Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
IBM8 citations73
US7089373B2Aug 8, 2006
Shadow register to enhance lock acquisition
IBM8 citations73
US7657667B2Feb 2, 2010
Method to provide cache management commands for a DMA controller
IBM5 citations63
US6961820B2Nov 1, 2005
System and method for identifying and accessing streaming data in a locked portion of a cache
IBM4 citations63
US7818509B2Oct 19, 2010
Combined response cancellation for load command
IBM2 citations62
US7814281B2Oct 12, 2010
Method to provide atomic update primitives in an asymmetric heterogeneous multiprocessor environment
IBM2 citations62
US7356713B2Apr 8, 2008
Method and apparatus for managing the power consumption of a data processing system
IBM4 citations62
US7353341B2Apr 1, 2008
System and method for canceling write back operation during simultaneous snoop push or snoop kill operation in write back caches
IBM2 citations61
US7836257B2Nov 16, 2010
System and method for cache line replacement selection in a multiprocessor environment
IBM3 citations60
US7725660B2May 25, 2010
Directory for multi-node coherent bus
IBM1 citations52
US7721123B2May 18, 2010
Method and apparatus for managing the power consumption of a data processing system
IBM0 citations52
US7877550B2Jan 25, 2011
Bus controller initiated write-through mechanism with hardware automatically generated clean command
IBM0 citations46
US7472229B2Dec 30, 2008
Bus controller initiated write-through mechanism
IBM0 citations46
US8015565B2Sep 6, 2011
Preventing livelocks in processor selection of load requests
IBM1 citations42
US7062612B2Jun 13, 2006
Updating remote locked cache
IBM0 citations42
US7120748B2Oct 10, 2006
Software-controlled cache set management
IBM0 citations39
QUALCOMM INC
3 patentsUS9990291B2Jun 5, 2018
Avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols
QUALCOMM INC0 citations48
US9594713B2Mar 14, 2017
Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media
QUALCOMM INC0 citations47
US9921962B2Mar 20, 2018
Maintaining cache coherency using conditional intervention among multiple master devices
QUALCOMM INC0 citations37