P

Inventor

GABOR ALLEN H

US40 patents
⚠️ This page may combine multiple inventors who share the name “GABOR ALLEN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

24 patents
US7001693B2Feb 21, 2006

Binary OPC for assist feature layout optimization

IBM70 citations98
US9472506B2Oct 18, 2016

Registration mark formation during sidewall image transfer process

IBM26 citations93
US7147976B2Dec 12, 2006

Binary OPC for assist feature layout optimization

IBM40 citations92
US6964032B2Nov 8, 2005

Pitch-based subresolution assist feature design

IBM26 citations92
US7799503B2Sep 21, 2010

Composite structures to prevent pattern collapse

IBM31 citations91
US7083898B1Aug 1, 2006

Method for performing chemical shrink process over BARC (bottom anti-reflective coating)

IBM11 citations84
US8361683B2Jan 29, 2013

Multi-layer chip overlay target and measurement

IBM5 citations73
US9859224B2Jan 2, 2018

Registration mark formation during sidewall image transfer process

IBM3 citations72
US7465615B1Dec 16, 2008

Polyconductor line end formation and related mask

IBM5 citations72
US7288478B2Oct 30, 2007

Method for performing chemical shrink process over BARC (bottom anti-reflective coating)

IBM5 citations71
US7993815B2Aug 9, 2011

Line ends forming

IBM3 citations63
US7914975B2Mar 29, 2011

Multiple exposure lithography method incorporating intermediate layer patterning

IBM3 citations63
US7354779B2Apr 8, 2008

Topography compensated film application methods

IBM4 citations62
US7541613B2Jun 2, 2009

Methods for reducing within chip device parameter variations

IBM2 citations60
US7493186B2Feb 17, 2009

Method and algorithm for the control of critical dimensions in a thermal flow process

IBM2 citations60
US7393703B2Jul 1, 2008

Method for reducing within chip device parameter variations

IBM5 citations60
US7479355B1Jan 20, 2009

Mask design for enhancing line end resolution

IBM5 citations59
US8847416B2Sep 30, 2014

Multi-layer chip overlay target and measurement

IBM0 citations52
US7968270B2Jun 28, 2011

Process of making a semiconductor device using multiple antireflective materials

IBM0 citations52
US7485573B2Feb 3, 2009

Process of making a semiconductor device using multiple antireflective materials

IBM1 citations52
US10242952B2Mar 26, 2019

Registration mark formation during sidewall image transfer process

IBM0 citations51
US10043760B2Aug 7, 2018

Registration mark formation during sidewall image transfer process

IBM0 citations51
US8592110B2Nov 26, 2013

Alignment marks for multi-exposure lithography

IBM0 citations51
US7727825B2Jun 1, 2010

Polyconductor line end formation and related mask

IBM1 citations51

GABOR ALLEN H

3 patents

CORNELL RES FOUNDATION INC

2 patents

ANGELOPOULOS MARIE

2 patents

BAILEY TODD CHRISTOPHER

2 patents

ARCH SPEC CHEM INC

1 patent

AGERE SYST GUARDIAN CORP

1 patent

RAGHUNATHAN SUDHARSHANAN

1 patent

INFINEON TECHNOLOGIES AG

1 patent

GLOBALFOUNDRIES INC

1 patent

BURKHARDT MARTIN

1 patent

AUSSCHNITT CHRISTOPHER P

1 patent