Inventor
CHENG CHUAN-CHENG
US29 patents
⚠️ This page may combine multiple inventors who share the name “CHENG CHUAN-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MARVELL INT LTD
12 patentsUS7808075B1Oct 5, 2010
Integrated circuit devices with ESD and I/O protection
MARVELL INT LTD47 citations97
US8044733B1Oct 25, 2011
Stress tolerant differential colpitts voltage controlled oscillators
MARVELL INT LTD19 citations92
US7704805B1Apr 27, 2010
Fuse structures, methods of making and using the same, and integrated circuits including the same
MARVELL INT LTD12 citations92
US7883947B1Feb 8, 2011
Method of fabricating a device with ESD and I/O protection
MARVELL INT LTD15 citations83
US7820493B1Oct 26, 2010
Methods of making and using fuse structures, and integrated circuits including the same
MARVELL INT LTD8 citations83
US6940107B1Sep 6, 2005
Fuse structures, methods of making and using the same, and integrated circuits including the same
MARVELL INT LTD8 citations73
US7589363B1Sep 15, 2009
Fuse structures, methods of making and using the same, and integrated circuits including the same
MARVELL INT LTD3 citations62
US7344924B1Mar 18, 2008
Fuse structures, methods of making and using the same, and integrated circuits including the same
MARVELL INT LTD2 citations62
US8372729B1Feb 12, 2013
Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same
MARVELL INT LTD2 citations61
US8049249B1Nov 1, 2011
Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same
MARVELL INT LTD3 citations61
US8753960B1Jun 17, 2014
Integrated circuit devices with electrostatic discharge (ESD) protection in scribe line regions
MARVELL INT LTD0 citations51
US8921938B1Dec 30, 2014
Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells
MARVELL INT LTD1 citations44
MARVELL WORLD TRADE LTD
6 patentsUS9768144B2Sep 19, 2017
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate
MARVELL WORLD TRADE LTD11 citations83
US10217669B2Feb 26, 2019
Isolation components for transistors formed on fin features of semiconductor substrates
MARVELL WORLD TRADE LTD3 citations73
US9275929B2Mar 1, 2016
Package assembly having a semiconductor substrate
MARVELL WORLD TRADE LTD6 citations73
US10784167B2Sep 22, 2020
Isolation components for transistors formed on fin features of semiconductor substrates
MARVELL WORLD TRADE LTD0 citations52
US9391045B2Jul 12, 2016
Recessed semiconductor substrates and associated techniques
MARVELL WORLD TRADE LTD0 citations51
US9397218B2Jul 19, 2016
Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices
MARVELL WORLD TRADE LTD0 citations42
LSI LOGIC CORP
3 patentsUS6495426B1Dec 17, 2002
Method for simultaneous formation of integrated capacitor and fuse
LSI LOGIC CORP16 citations92
US6627968B2Sep 30, 2003
Integrated capacitor and fuse
LSI LOGIC CORP10 citations74
US6815342B1Nov 9, 2004
Low resistance metal interconnect lines and a process for fabricating them
LSI LOGIC CORP5 citations61
WU ALBERT
3 patentsUS8861214B1Oct 14, 2014
High resistivity substrate for integrated passive device (IPD) applications
WU ALBERT4 citations73
US9257410B2Feb 9, 2016
Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate
WU ALBERT2 citations62
US9034730B2May 19, 2015
Recessed semiconductor substrates and associated techniques
WU ALBERT0 citations51