Inventor
UNDY STEPHEN R
US17 patents
⚠️ This page may combine multiple inventors who share the name “UNDY STEPHEN R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HEWLETT PACKARD DEVELOPMENT CO
10 patentsUS6721875B1Apr 13, 2004
Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form
HEWLETT PACKARD DEVELOPMENT CO84 citations97
US6799263B1Sep 28, 2004
Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted
HEWLETT PACKARD DEVELOPMENT CO70 citations94
US7343479B2Mar 11, 2008
Method and apparatus for implementing two architectures in a chip
HEWLETT PACKARD DEVELOPMENT CO18 citations92
US6678817B1Jan 13, 2004
Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine
HEWLETT PACKARD DEVELOPMENT CO23 citations89
US6883150B2Apr 19, 2005
Automatic manufacturing test case generation method and system
HEWLETT PACKARD DEVELOPMENT CO19 citations87
US6711671B1Mar 23, 2004
Non-speculative instruction fetch in speculative processing
HEWLETT PACKARD DEVELOPMENT CO14 citations84
US6944751B2Sep 13, 2005
Register renaming to reduce bypass and increase apparent physical register size
HEWLETT PACKARD DEVELOPMENT CO12 citations83
US6647487B1Nov 11, 2003
Apparatus and method for shift register rate control of microprocessor instruction prefetches
HEWLETT PACKARD DEVELOPMENT CO12 citations73
US6618801B1Sep 9, 2003
Method and apparatus for implementing two architectures in a chip using bundles that contain microinstructions and template information
HEWLETT PACKARD DEVELOPMENT CO10 citations73
US7356674B2Apr 8, 2008
Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine
HEWLETT PACKARD DEVELOPMENT CO0 citations48
HEWLETT PACKARD CO
7 patentsUS5751735AMay 12, 1998
Integrated debug trigger method and apparatus for an integrated circuit
HEWLETT PACKARD CO96 citations95
US5860097AJan 12, 1999
Associative cache memory with improved hit time
HEWLETT PACKARD CO27 citations92
US6516388B1Feb 4, 2003
Method and apparatus for reducing cache pollution
HEWLETT PACKARD CO12 citations73
US5961655AOct 5, 1999
Opportunistic use of pre-corrected data to improve processor performance
HEWLETT PACKARD CO12 citations72
US5860096AJan 12, 1999
Multi-level instruction cache for a computer
HEWLETT PACKARD CO15 citations72
US6493792B1Dec 10, 2002
Mechanism for broadside reads of CAM structures
HEWLETT PACKARD CO5 citations62
US5829049AOct 27, 1998
Simultaneous execution of two memory reference instructions with only one address calculation
HEWLETT PACKARD CO6 citations58