Inventor

CLEEVES JAMES M

US106 patents

⚠️ This page may combine multiple inventors who share the name “CLEEVES JAMES M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CLEEVES JAMES M

MATRIX SEMICONDUCTOR INC

Electrically isolated pillars in active devices

Monolithic three dimensional array of charge storage devices containing a planarized surface

Multigate semiconductor device with vertical channel current and method of fabrication

Patterning three dimensional structures

Multigate semiconductor device with vertical channel current and method of fabrication

Formation of antifuse structure in a three dimensional memory

Vertically stacked field programmable nonvolatile memory and method of fabrication

Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

Integrated circuit structure including three-dimensional memory array

Vertically stacked field programmable nonvolatile memory and method of fabrication

Vertically stacked field programmable nonvolatile memory and method of fabrication

Vertically stacked field programmable nonvolatile memory and method of fabrication

Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions

Anti-fuse memory cell with asymmetric breakdown voltage

Contact and via structure and method of fabrication

Three-dimensional memory array and method for storing data bits and ECC bits therein

Memory device and method for sensing while programming a non-volatile memory cell

Method and system for increasing programming bandwidth in a non-volatile memory device

Method of forming nonvolatile memory device utilizing a hard mask

Method of generating integrated circuit feature layout for improved chemical mechanical polishing

Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Memory array organization and related test method particularly well suited for integrated circuits having write-once memory arrays

Dummy wafers and methods for making the same

SANDISK 3D LLC

Three-dimensional memory

Dense arrays and charge storage devices

Three terminal nonvolatile memory device with vertical gated diode

Dense arrays and charge storage devices

Dense arrays and charge storage devices

Vertically stacked field programmable nonvolatile memory and method of fabrication

Integrated circuit incorporating three-dimensional memory array with dual opposing decoder arrangement

Vertically stacked field programmable nonvolatile memory and method of fabrication

Memory cell with high-K antifuse for reverse bias programming

Vertically stacked field programmable nonvolatile memory and method of fabrication

Three-dimensional memory

CYPRESS SEMICONDUCTOR CORP

Self-aligned trench isolated structure

Method of making an antifuse metal post structure

Method for reduced pitch lithography

Disposable posts for self-aligned non-enclosed contacts

Thin liner layer providing reduced via resistance

Method for forming an interconnect

Interconnect methods and apparatus

Encapsulated dielectric and method of fabrication

Disposable post processing for semiconductor device fabrication

Method for reduced pitch lithography

CANDESCENT TECH CORP

Patterned resistor suitable for electron-emitting device

Fabrication of gated electron-emitting device utilizing distributed particles to define gate openings, typically in combination with spacer material to control spacing between gate layer and electron-emissive elements

CLEEVES ENGINES INC

Internal combustion engine

MATRIX SEMICONDUCTOR

Method of making a contact and via structure

SANDISK CORP

Vertically stacked field programmable nonvolatile memory and method of fabrication

SANDISCK 3D LLC

Optimization of critical dimensions and pitch of patterned features in and above a substrate