Inventor
CHEN MIN-LIANG
TW32 patents
⚠️ This page may combine multiple inventors who share the name “CHEN MIN-LIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MOSEL VITELIC INC
21 patentsUS5827747AOct 27, 1998
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation
MOSEL VITELIC INC69 citations96
US6100561AAug 8, 2000
Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation
MOSEL VITELIC INC21 citations92
US5930631AJul 27, 1999
Method of making double-poly MONOS flash EEPROM cell
MOSEL VITELIC INC50 citations92
US5885866AMar 23, 1999
Self-registered cylindrical capacitor of high density DRAMs
MOSEL VITELIC INC41 citations92
US5789297AAug 4, 1998
Method of making EEPROM cell device with polyspacer floating gate
MOSEL VITELIC INC38 citations92
US5703388ADec 30, 1997
Double-poly monos flash EEPROM cell
MOSEL VITELIC INC43 citations92
US5686324ANov 11, 1997
Process for forming LDD CMOS using large-tilt-angle ion implantation
MOSEL VITELIC INC37 citations92
US5679595AOct 21, 1997
Self-registered capacitor bottom plate-local interconnect scheme for DRAM
MOSEL VITELIC INC37 citations92
US5514609AMay 7, 1996
Through glass ROM code implant to reduce product delivering time
MOSEL VITELIC INC18 citations79
US5966632AOct 12, 1999
Method of forming borderless metal to contact structure
MOSEL VITELIC INC19 citations77
US6100126AAug 8, 2000
Method of making a resistor utilizing a polysilicon plug formed with a high aspect ratio
MOSEL VITELIC INC10 citations74
US6020231AFeb 1, 2000
Method for forming LDD CMOS
MOSEL VITELIC INC15 citations74
US5926712AJul 20, 1999
Process for fabricating MOS device having short channel
MOSEL VITELIC INC16 citations73
US5792686AAug 11, 1998
Method of forming a bit-line and a capacitor structure in an integrated circuit
MOSEL VITELIC INC15 citations73
US5691223ANov 25, 1997
Method of fabricating a capacitor over a bit line DRAM process
MOSEL VITELIC INC15 citations73
US5681772AOct 28, 1997
Through glass ROM code implant to reduce product delivering time
MOSEL VITELIC INC10 citations71
US6107193AAug 22, 2000
Completely removal of TiN residue on dual damascence process
MOSEL VITELIC INC12 citations66
US6271556B1Aug 7, 2001
High density memory structure
MOSEL VITELIC INC3 citations62
US5880496AMar 9, 1999
Semiconductor having self-aligned polysilicon electrode layer
MOSEL VITELIC INC4 citations62
US5691562ANov 25, 1997
Through glass ROM code implant to reduce product delivering time
MOSEL VITELIC INC2 citations60
US5972746AOct 26, 1999
Method for manufacturing semiconductor devices using double-charged implantation
MOSEL VITELIC INC1 citations51
AT & T BELL LAB
7 patentsUS5290720AMar 1, 1994
Transistor with inverse silicide T-gate structure
AT & T BELL LAB85 citations96
US5200358AApr 6, 1993
Integrated circuit with planar dielectric layer
AT & T BELL LAB58 citations94
US5322807AJun 21, 1994
Method of making thin film transistors including recrystallization and high pressure oxidation
AT & T BELL LAB40 citations93
US4905073AFeb 27, 1990
Integrated circuit with improved tub tie
AT & T BELL LAB65 citations93
US5102827AApr 7, 1992
Contact metallization of semiconductor integrated-circuit devices
AT & T BELL LAB24 citations92
US5045898ASep 3, 1991
CMOS integrated circuit having improved isolation
AT & T BELL LAB22 citations92
US4996167AFeb 26, 1991
Method of making electrical contacts to gate structures in integrated circuits
AT & T BELL LAB32 citations92