Inventor

BARTH JR JOHN E

US82 patents

⚠️ This page may combine multiple inventors who share the name “BARTH JR JOHN E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BARTH JR JOHN E

IBM

Dynamic ram with on-chip ecc and optimized bit and word redundancy

Faulty core recovery mechanisms for a three-dimensional network on a processor array

System and method for capacitive mis-match bit-line sensing

Low-cost deep trench decoupling capacitor device and process of manufacture

ECC based system and method for repairing failed memory elements

Concurrent refresh mode with distributed row address counters in an embedded DRAM

Direct read of DRAM cell using high transfer ratio

Secure and dense SRAM cells in EDRAM technology

System and method for early write to memory by holding bitline at fixed potential

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Bi-mode sense amplifier with dual utilization of the reference cells and dual precharge scheme for improving data retention

Self timing interlock circuit for embedded DRAM

Twin-cell memory architecture with shielded bitlines for embedded memory applications

Array of processor core circuits with reversible tiers

Signal margin centering for single-ended eDRAM sense amplifier

Final faulty core recovery mechanisms for a two-dimensional network on a processor array

Power connector/decoupler integrated in a heat sink

Low overhead switched header power savings apparatus

Method for reduced electrical fusing time

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Memory BIST and repair

Electronic circuit for remapping faulty memory arrays of variable size

Flexible multibanking interface for embedded memory applications

Column redundancy system and method for embedded DRAM devices with multibanking capability

System and method for early write to memory by injecting small voltage signal

Method for setting test voltages in a flash write mode

Interconnect circuits at three dimensional (3-D) bonding interfaces of a processor array

Vertically integrated memory cell

Reduced stress high voltage word line driver

Semiconductor-on-insulator (SOI) deep trench capacitor

Array organization and architecture to perform range-match operations with content addressable memory (CAM) circuits

Providing transposable access to a synapse array using a recursive array layout

Capacitively isolated mismatch compensated sense amplifier

Soft error protection structure employing a deep trench

Memory cell access circuit

Dynamic random access memory circuit, design structure and method

Low overhead switched header power savings apparatus

Memory cell access circuit

System and method for implementing self-timed decoded data paths in integrated circuits

System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch

BARTH JR JOHN E

Deep trench electrostatic discharge (ESD) protect diode for silicon-on-insulator (SOI) devices

Reference level generation with offset compensation for sense amplifier

Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods

Metal-insulator-metal (MIM) capacitor with deep trench (DT) structure and method in a silicon-on-insulator (SOI)

VDD pre-set of direct sense DRAM

Vertical through-silicon via for a semiconductor structure

ARTHUR JOHN V

Providing transposable access to a synapse array using a recursive array layout

Providing transposable access to a synapse array using column aggregation

ANDERSON BRENT A

FET eDRAM trench self-aligned to buried strap

GLOBALFOUNDRIES INC

Vertical fin eDRAM