Inventor

KEGEL ANDREW G

US47 patents

⚠️ This page may combine multiple inventors who share the name “KEGEL ANDREW G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KEGEL ANDREW G

ADVANCED MICRO DEVICES INC

Scheduling of data migration

Virtual FPGA management and optimization system

I/O memory management unit including multilevel address translation for I/O and computation offload

Using processor types for processing interrupts in a computing device

Method and apparatus for reducing TLB shootdown overheads in accelerator-based systems

Efficiently controlling special memory mapped system accesses

Protecting memory contents during boot process

Secure computer system for preventing access requests to portions of system memory by peripheral devices and/or processor cores

Protecting host memory from access by untrusted accelerators

Self-regulating power management for a neural network system

Self-regulating power management for a neural network system

Shareable FPGA compute engine

Enhanced page information co-processor

Method and apparatus for efficient programmable instructions in computer systems

Enhanced method for a useful blockchain consensus

Enhanced page information co-processor

Method and apparatus for efficient programmable instructions in computer systems

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

System and method of managing electronic meeting invitations

Adaptive extension of leases for entries in a translation lookaside buffer

Setting durations for which data is stored in a non-volatile memory based on data types

Setting durations for which data is stored in a non-volatile memory based on data types

Using multiple memory elements in an input-output memory management unit for performing virtual address to physical address translations

Using leases for entries in a translation lookaside buffer

Resizable and relocatable queue

Techniques for identifying and handling processor interrupts

Extensible I/O activity logs

Virtual interrupt filter

Separating temperature domains in cooled systems

Systems and methods for trusted cluster attestation

Routing direct memory access requests in a virtualized computing environment

Relocatable and resizable tables in a computing device

Non-volatile hybrid memory

KEGEL ANDREW G

Input/output memory management unit with protection mode for preventing memory access by I/O devices

Virtual input/output memory management unit within a guest virtual machine

IOMMU using two-level address translation for I/O and computation offload devices on a peripheral interconnect

All invalidate approach for memory management units

Server discovery, spawning collector threads to collect information from servers, and reporting information

Method and apparatus for remapping interrupt types

Method and apparatus for controlling system interrupts

IBM

Method for discovering servers, spawning collector threads to collect information from servers, and reporting information

Trust evaluation

Trust evaluation

GLOBALFOUNDRIES INC

Filtering and remapping interrupts

Translation data prefetch in an IOMMU

BADE STEVEN A

Trusted platform module data harmonization during trusted server rendevous

HUMMEL MARK D

Mechanism to handle peripheral page faults