Inventor

VAN BRUNT EDWARD ROBERT

US38 patents

⚠️ This page may combine multiple inventors who share the name “VAN BRUNT EDWARD ROBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN BRUNT EDWARD ROBERT

WOLFSPEED INC

Alignment for wafer images

Nondestructive characterization for crystalline wafers

Device design for short-circuit protection of transistors

Edge termination structures for semiconductor devices

Protection structures for semiconductor devices with sensor arrangements

Transistor semiconductor die with increased active area

Superjunction power semiconductor devices formed via ion implantation channeling techniques and related methods

Semiconductor devices for improved measurements and related methods

Edge termination structures for semiconductor devices

Device design for short-circuitry protection circuitry within transistors

Vertical semiconductor device with improved ruggedness

Power semiconductor device with reduced strain

Vertical semiconductor device with improved ruggedness

Wide bandgap semiconductor device with sensor element

Nondestructive characterization for crystalline wafers

Power semiconductor device with reduced strain

Vertical semiconductor device with improved ruggedness

Semiconductor device with selectively grown field oxide layer in edge termination region

Multi-scale autoencoders for semiconductor workpiece understanding

Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices

CREE INC

Methods and apparatuses related to shaping wafers fabricated by ion implantation

Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions

Layout configurations for integrating schottky contacts into a power transistor device

Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods

Seminconductor device with spreading layer

Methods of forming power semiconductor devices having superjunction structures with pillars having implanted sidewalls

Power semiconductor devices having superjunction structures with implanted sidewalls

Edge termination technique for high voltage power devices having a negative feature for an improved edge termination structure

Hybrid power module

Contact structures for semiconductor devices

Transistor semiconductor die with increased active area

Methods of forming junction termination extension edge terminations for high power semiconductor devices and related semiconductor devices

Power semiconductor devices having top-side metallization structures that include buried grain stop layers

Monolithically integrated vertical power transistor and bypass diode

Methods of forming buried junction devices in silicon carbide using ion implant channeling and silicon carbide devices including buried junctions

Semiconductor devices in SiC using vias through N-type substrate for backside contact to P-type layer

Vertical semiconductor device with improved ruggedness

Semiconductor device including a power transistor device and bypass diode