Inventor

LECLER JEAN-JACQUES

US22 patents

⚠️ This page may combine multiple inventors who share the name “LECLER JEAN-JACQUES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LECLER JEAN-JACQUES

QUALCOMM TECHNOLOGIES INC

Three channel cache-coherency socket protocol

Method and apparatus for supporting target-side security in a cache coherent system

Network on a chip socket protocol

DMA engine with STLB prefetch capabilities and tethered prefetching

System translation look-aside buffer integrated in an interconnect

System translation look-aside buffer with request-based allocation and prefetching

Automatic pipeline stage insertion

Zero-latency network on chip (NoC)

Adaptive tuning of snoops

Three channel cache-coherency socket protocol

Network on a chip socket protocol

QUALCOMM INC

Dynamic memory scheduling routine with enhanced bank-group batching

Dram-aware caching

Memory bank group interleaving

Method and apparatus for ternary mapping

BOUCARD PHILIPPE

Network on chip (NoC) with QoS features

System and method of distributed initiator-local reorder buffers

Transport of PCI-ordered traffic over independent networks

ARTERIS

Digital delay device, digital oscillator clock signal generator and memory interface

MOLL LAURENT

Coherency controller with reduced data buffer

Arteris SAS

Differential formatting between normal and retry data transmission

LECLER JEAN-JACQUES

Zero-latency network on chip (NoC)